Issued Patents All Time
Showing 101–125 of 140 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8865523 | Semiconductor package and fabrication method thereof | Yueh-Se Ho, Jun Lu, Lei Shi, Liang Zhao, Ping Huang | 2014-10-21 |
| 8853003 | Wafer level chip scale package with thick bottom metal exposed and preparation method thereof | — | 2014-10-07 |
| 8841167 | Manufacturing method of a semiconductor package of small footprint with a stack of lead frame die paddle sandwiched between high-side and low-side MOSFET | Yuping Gong, Liang Zhao | 2014-09-23 |
| 8785296 | Packaging method with backside wafer dicing | Ping Huang, Yueh-Se Ho | 2014-07-22 |
| 8778735 | Packaging method of molded wafer level chip scale package (WLCSP) | Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Ping Huang, Lei Shi +2 more | 2014-07-15 |
| 8722466 | Semiconductor packaging and fabrication method using connecting plate for internal connection | Jun Lu, Kai Liu | 2014-05-13 |
| 8722467 | Method of using bonding ball array as height keeper and paste holder in semiconductor device package | Lei Shi, Aihua Lu | 2014-05-13 |
| 8722468 | Semiconductor encapsulation method | Anup Bhalla, Jun Lu | 2014-05-13 |
| 8716069 | Semiconductor device employing aluminum alloy lead-frame with anodized aluminum | Yueh-Se Ho, Yongping Ding | 2014-05-06 |
| 8710648 | Wafer level packaging structure with large contact area and preparation method thereof | — | 2014-04-29 |
| 8703545 | Aluminum alloy lead-frame and its use in fabrication of power semiconductor package | Zhiqiang Niu, Ming-Chen Lu, Yan Huo, Hua Pan, Guo Feng Lian +1 more | 2014-04-22 |
| 8686546 | Combined packaged power semiconductor device | Yueh-Se Ho, Hamza Yilmaz, Jun Lu | 2014-04-01 |
| 8642385 | Wafer level package structure and the fabrication method thereof | Ping Huang, Yueh-Se Ho, Hamza Yilmaz, Jun Lu, Ming-Chen Lu | 2014-02-04 |
| 8642397 | Semiconductor wafer level package (WLP) and method of manufacture thereof | Yuping Gong, Ping Huang | 2014-02-04 |
| 8586414 | Top exposed package and assembly method | Yueh-Se Ho, Hamza Yilmaz, Anup Bhalla, Jun Lu, Kal Liu | 2013-11-19 |
| 8581376 | Stacked dual chip package and method of fabrication | Hamza Yilmaz, Xiaotian Zhang, Anup Bhalla, Jun Lu, Kai Liu +2 more | 2013-11-12 |
| 8575006 | Process to form semiconductor packages with external leads | Jun Lu | 2013-11-05 |
| 8569169 | Bottom source power MOSFET with substrateless and manufacturing method thereof | Yueh-Se Ho, Ping Huang | 2013-10-29 |
| 8563361 | Packaging method of molded wafer level chip scale package (WLCSP) | Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Ping Huang, Lei Shi +2 more | 2013-10-22 |
| 8563417 | Method for packaging ultra-thin chip with solder ball thermo-compression in wafer level packaging process | Jun Lu, Alex Niu, Yueh-Se Ho, Ping Hoang, Jacky Gong +2 more | 2013-10-22 |
| 8564110 | Power device with bottom source electrode | Yueh-Se Ho, Hamza Yilmaz, Jun Lu, Lei Shi, Liang Zhao +1 more | 2013-10-22 |
| 8519520 | Semiconductor package of small footprint with a stack of lead frame die paddle sandwich between high-side and low-side MOSFETs and manufacturing method | Yuping Gong, Liang Zhao | 2013-08-27 |
| 8519525 | Semiconductor encapsulation and method thereof | Anup Bhalla, Jun Lu | 2013-08-27 |
| 8482048 | Metal oxide semiconductor field effect transistor integrating a capacitor | Anup Bhalla, Hamza Yilmaz, Jun Lu | 2013-07-09 |
| 8481368 | Semiconductor package of a flipped MOSFET and its manufacturing method | Yueh-Se Ho, Hamza Yilmaz, Jun Lu | 2013-07-09 |