Issued Patents 2023
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854987 | Semiconductor packages with interconnection features in a seal region and methods for forming the same | Ming-Han Lee, Shin-Yi Yang | 2023-12-26 |
| 11854963 | Semiconductor interconnection structure and methods of forming the same | Shao-Kuan Lee, Kuang-Wei YANG, Cherng-Shiaw Tsai, Cheng-Chin Lee, Ting-Ya Lo +3 more | 2023-12-26 |
| 11854944 | Semiconductor packages and methods for forming the same | Shin-Yi Yang, Ming-Han Lee | 2023-12-26 |
| 11854820 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee +6 more | 2023-12-26 |
| 11848190 | Barrier-less structures | Hsin-Ping Chen, Yung-Hsu Wu, Chia-Tien Wu, Min Cao, Ming-Han Lee +1 more | 2023-12-19 |
| 11810815 | Dielectric capping structure overlying a conductive structure to increase stability | Hsin-Yen Huang, Chi-Lin Teng, Hai-Ching Chen, Shao-Kuan Lee, Cheng-Chin Lee +1 more | 2023-11-07 |
| 11769695 | Semiconductor structure including low-resistance interconnect and integrated circuit device having the same | Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hsiang-Wei Liu, Tai-I Yang +2 more | 2023-09-26 |
| 11764106 | Semiconductor device and method of manufacture | Tai-I Yang, Wei-Chen Chu, Yung-Chih Wang, Chia-Tien Wu, Hsin-Ping Chen | 2023-09-19 |
| 11756878 | Self-aligned via structure by selective deposition | Shao-Kuan Lee, Hsin-Yen Huang, Cheng-Chin Lee, Hai-Ching Chen | 2023-09-12 |
| 11749643 | Semiconductor packages and methods for forming the same | Shin-Yi Yang, Ming-Han Lee | 2023-09-05 |
| 11742239 | Methods of performing chemical-mechanical polishing process in semiconductor devices | Shih-Kang Fu, Ming-Han Lee | 2023-08-29 |
| 11735513 | Integrated chip having a back-side power rail | Shin-Yi Yang, Ming-Han Lee | 2023-08-22 |
| 11728264 | Hybrid interconnect structure for self aligned via | Shin-Yi Yang, Ming-Han Lee | 2023-08-15 |
| 11721627 | Graphene layer for reduced contact resistance | Shin-Yi Yang, Ming-Han Lee | 2023-08-08 |
| 11715689 | Method of forming metal interconnection | Shin-Yi Yang, Ming-Han Lee, Tz-Jun Kuo | 2023-08-01 |
| 11710700 | Graphene-assisted low-resistance interconnect structures and methods of formation thereof | Shin-Yi Yang, Yu-Chen Chan, Ming-Han Lee, Hai-Ching Chen | 2023-07-25 |
| 11670595 | Semiconductor device structure and methods of forming the same | Yu-Chen Chan, Shu-Wei Li, Shin-Yi Yang, Ming-Han Lee | 2023-06-06 |
| 11658092 | Thermal interconnect structure for thermal management of electrical interconnect structure | Shao-Kuan Lee, Cherng-Shiaw Tsai, Ting-Ya Lo, Cheng-Chin Lee, Chi-Lin Teng +3 more | 2023-05-23 |
| 11652055 | Interconnect structure with hybrid barrier layer | Shu-Wei Li, Shin-Yi Yang, Ming-Han Lee | 2023-05-16 |
| 11640928 | Heat dispersion layers for double sided interconnect | Hsin-Yen Huang, Shao-Kuan Lee, Hsiao-Kang Chang, Cherng-Shiaw Tsai | 2023-05-02 |
| 11640940 | Methods of forming interconnection structure including conductive graphene layers | Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee | 2023-05-02 |
| 11640924 | Structure and method for interconnection with self-alignment | Tai-I Yang, Yu-Chieh Liao, Chia-Tien Wu, Hsin-Ping Chen, Hai-Ching Chen | 2023-05-02 |
| 11594483 | Semiconductor structure | Shin-Yi Yang, Ming-Han Lee | 2023-02-28 |
| 11569124 | Interconnect structure having an etch stop layer over conductive lines | Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao | 2023-01-31 |
| 11557511 | Semiconductor device structure and methods of forming the same | Hsin-Yen Huang, Ting-Ya Lo, Shao-Kuan Lee, Chi-Lin Teng, Cheng-Chin Lee +1 more | 2023-01-17 |