Issued Patents 2020
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10847635 | Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices | Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Stephen M. Cea +1 more | 2020-11-24 |
| 10840366 | Nanowire structures having wrap-around contacts | Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Michael Haverty, Sadasivan Shankar | 2020-11-17 |
| 10825752 | Integrated thermoelectric cooling | Lei Jiang, Edwin B. Ramayya, Daniel Pantuso, Rafael Rios, Kelin J. Kuhn | 2020-11-03 |
| 10804357 | Integration methods to fabricate internal spacers for nanowire devices | Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2020-10-13 |
| 10784352 | Method to achieve a uniform Group IV material layer in an aspect ratio trapping trench | Sanaz K. Gardner, Willy Rachmady, Van H. Le, Matthew V. Metz, Ashish Agrawal +1 more | 2020-09-22 |
| 10770458 | Nanowire transistor device architectures | Rishabh Mehandru, Tahir Ghani, Szuya S. Liao | 2020-09-08 |
| 10672868 | Methods of forming self aligned spacers for nanowire device structures | Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Jun Sung Kang | 2020-06-02 |
| 10636871 | Silicon and silicon germanium nanowire structures | Kelin J. Kuhn, Rafael Rios, Stephen M. Cea, Martin D. Giles, Annalisa Cappellani +3 more | 2020-04-28 |
| 10593785 | Transistors having ultra thin fin profiles and their methods of fabrication | Sanaz K. Gardner, Willy Rachmady, Van H. Le, Matthew V. Metz, Ashish Agrawal +1 more | 2020-03-17 |
| 10593804 | Non-planar semiconductor device having hybrid geometry-based active region | Rafael Rios, Fahmida Ferdousi, Kelin J. Kuhn | 2020-03-17 |
| 10586868 | Non-planar semiconductor device having hybrid geometry-based active region | Rafael Rios, Fahmida Ferdousi, Kelin J. Kuhn | 2020-03-10 |
| 10580899 | Nanowire structures having non-discrete source and drain regions | Stephen M. Cea, Annalisa Cappellani, Martin D. Giles, Rafael Rios, Kelin J. Kuhn | 2020-03-03 |
| 10580882 | Low band gap semiconductor devices having reduced gate induced drain leakage (GIDL) | Gilbert Dewey, Jack T. Kavalieros, Willy Rachmady, Matthew V. Metz, Van H. Le +1 more | 2020-03-03 |
| 10580860 | Integration methods to fabricate internal spacers for nanowire devices | Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2020-03-03 |
| 10573750 | Methods of forming doped source/drain contacts and structures formed thereby | Glenn A. Glass, Karthik Jambunathan, Anand S. Murthy, Chandra S. Mohapatra | 2020-02-25 |