Issued Patents 2020
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10878889 | High retention time memory element with dual gate devices | Rafael Rios, Gilbert Dewey, Van H. Le, Mesut Meterelliyoz | 2020-12-29 |
| 10879365 | Transistors with non-vertical gates | Cheng-Ying Huang, Sean T. Ma, Willy Rachmady, Gilbert Dewey, Matthew V. Metz +3 more | 2020-12-29 |
| 10847656 | Fabrication of non-planar IGZO devices for improved electrostatics | Van H. Le, Gilbert Dewey, Rafael Rios, Marko Radosavljevic, Kent Millard +4 more | 2020-11-24 |
| 10847619 | Supperlatice channel included in a trench | Cheng-Ying Huang, Matthew V. Metz, Willy Rachmady, Gilbert Dewey | 2020-11-24 |
| 10840352 | Nanowire transistors with embedded dielectric spacers | Willy Rachmady, Seung Hoon Sung, Sanaz K. Gardner | 2020-11-17 |
| 10818793 | Indium-rich NMOS transistor channels | Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Willy Rachmady +3 more | 2020-10-27 |
| 10797150 | Differential work function between gate stack metals to reduce parasitic capacitance | Sean T. Ma, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey +3 more | 2020-10-06 |
| 10784352 | Method to achieve a uniform Group IV material layer in an aspect ratio trapping trench | Sanaz K. Gardner, Willy Rachmady, Van H. Le, Matthew V. Metz, Seiyon Kim +1 more | 2020-09-22 |
| 10784360 | Transistor gate trench engineering to decrease capacitance and resistance | Seung Hoon Sung, Willy Rachmady, Han Wui Then, Marko Radosavljevic | 2020-09-22 |
| 10784170 | CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture | Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Willy Rachmady +4 more | 2020-09-22 |
| 10770593 | Beaded fin transistor | Gilbert Dewey, Tahir Ghani, Willy Rachmady, Matthew V. Metz, Anand S. Murthy +1 more | 2020-09-08 |
| 10756198 | Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same | Gilbert Dewey, Niloy Mukherjee, Matthew V. Metz, Nancy Zelick, Robert S. Chau | 2020-08-25 |
| 10748993 | Strain compensation in transistors | Van H. Le, Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Ravi Pillarisetty | 2020-08-18 |
| 10749032 | Techniques for forming transistors including group III-V material nanowires using sacrificial group IV material layers | Chandra S. Mohapatra, Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Willy Rachmady +2 more | 2020-08-18 |
| 10748900 | Fin-based III-V/SI or GE CMOS SAGE integration | Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Chandra S. Mohapatra, Anand S. Murthy +1 more | 2020-08-18 |
| 10734488 | Aluminum indium phosphide subfin germanium channel transistors | Matthew V. Metz, Willy Rachmady, Harold W. Kennel, Van H. Le, Benjamin Chu-Kung +1 more | 2020-08-04 |
| 10734513 | Heterojunction TFETs employing an oxide semiconductor | Prashant Majhi, Elijah V. Karpov, Uday Shah, Ravi Pillarisetty | 2020-08-04 |
| 10734511 | High mobility asymmetric field effect transistors with a band-offset semiconductor drain spacer | Cheng-Ying Huang, Willy Rachmady, Matthew V. Metz, Benjamin Chu-Kung, Gilbert Dewey +1 more | 2020-08-04 |
| 10727339 | Selectively regrown top contact for vertical semiconductor devices | Benjamin Chu-Kung, Gilbert Dewey, Van H. Le, Marko Radosavljevic, Ravi Pillarisetty +3 more | 2020-07-28 |
| 10692973 | Germanium-rich channel transistors including one or more dopant diffusion barrier elements | Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Benjamin Chu-Kung, Seung Hoon Sung +2 more | 2020-06-23 |
| 10693008 | Cladding layer epitaxy via template engineering for heterogeneous integration on silicon | Niloy Mukherjee, Marko Radosavljevic, Ravi Pillarisetty, Niti Goel, Van H. Le +2 more | 2020-06-23 |
| 10665688 | Low Schottky barrier contact structure for Ge NMOS | Willy Rachmady, Matthew V. Metz, Benjamin Chu-Kung, Van H. Le, Gilbert Dewey +1 more | 2020-05-26 |
| 10659046 | Local cell-level power gating switch | Rafael Rios, Van H. Le, Gilbert Dewey | 2020-05-19 |
| 10651313 | Reduced transistor resistance using doped layer | Cheng-Ying Huang, Matthew V. Metz, Gilbert Dewey, Willy Rachmady, Sean T. Ma | 2020-05-12 |
| 10651288 | Pseudomorphic InGaAs on GaAs for gate-all-around transistors | Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Willy Rachmady, Gilbert Dewey +2 more | 2020-05-12 |