Issued Patents 2020
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10878889 | High retention time memory element with dual gate devices | Gilbert Dewey, Van H. Le, Jack T. Kavalieros, Mesut Meterelliyoz | 2020-12-29 |
| 10847653 | Semiconductor device having metallic source and drain regions | Martin D. Giles, Annalisa Cappellani, Sanaz K. Gardner, Cory E. Weber, Aaron A. Budrevich | 2020-11-24 |
| 10847656 | Fabrication of non-planar IGZO devices for improved electrostatics | Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Marko Radosavljevic, Kent Millard +4 more | 2020-11-24 |
| 10825752 | Integrated thermoelectric cooling | Lei Jiang, Edwin B. Ramayya, Daniel Pantuso, Kelin J. Kuhn, Seiyon Kim | 2020-11-03 |
| 10804357 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong +2 more | 2020-10-13 |
| 10734511 | High mobility asymmetric field effect transistors with a band-offset semiconductor drain spacer | Cheng-Ying Huang, Willy Rachmady, Jack T. Kavalieros, Matthew V. Metz, Benjamin Chu-Kung +1 more | 2020-08-04 |
| 10727138 | Integration of single crystalline transistors in back end of line (BEOL) | Van H. Le, Marko Radosavljevic, Benjamin Chu-Kung, Gilbert Dewey | 2020-07-28 |
| 10659046 | Local cell-level power gating switch | Van H. Le, Gilbert Dewey, Jack T. Kavalieros | 2020-05-19 |
| 10644140 | Integrated circuit die having back-end-of-line transistors | Van H. Le, Gilbert Dewey, Marko Radosavljevic, Jack T. Kavalieros | 2020-05-05 |
| 10644111 | Strained silicon layer with relaxed underlayer | Benjamin Chu-Kung, Van H. Le, Ashish Agrawal, Jack T. Kavalieros, Matthew V. Metz +2 more | 2020-05-05 |
| 10644123 | Systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors | Gilbert Dewey, Van H. Le, Jack T. Kavalieros, Shriram Shivaraman | 2020-05-05 |
| 10636871 | Silicon and silicon germanium nanowire structures | Kelin J. Kuhn, Seiyon Kim, Stephen M. Cea, Martin D. Giles, Annalisa Cappellani +3 more | 2020-04-28 |
| 10593804 | Non-planar semiconductor device having hybrid geometry-based active region | Seiyon Kim, Fahmida Ferdousi, Kelin J. Kuhn | 2020-03-17 |
| 10586868 | Non-planar semiconductor device having hybrid geometry-based active region | Seiyon Kim, Fahmida Ferdousi, Kelin J. Kuhn | 2020-03-10 |
| 10580899 | Nanowire structures having non-discrete source and drain regions | Stephen M. Cea, Annalisa Cappellani, Martin D. Giles, Seiyon Kim, Kelin J. Kuhn | 2020-03-03 |
| 10580860 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong +2 more | 2020-03-03 |
| 10535770 | Scaled TFET transistor formed using nanowire with surface termination | Uygar E. Avci, Kelin J. Kuhn, Ian A. Young, Justin R. Weber | 2020-01-14 |