Issued Patents 2020
Showing 301–325 of 332 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10553495 | Nanosheet transistors with different gate dielectrics and workfunction metals | Choonghyun Lee, Juntao Li, Peng Xu | 2020-02-04 |
| 10553493 | Fabrication of a vertical transistor with self-aligned bottom source/drain | Xin Miao, Wenyu Xu, Chen Zhang | 2020-02-04 |
| 10553445 | Stacked nanowires | Zhenxing Bi, Juntao Li, Xin Miao | 2020-02-04 |
| 10546788 | Dual channel FinFETs having uniform fin heights | Zhenxing Bi, Peng Xu, Jie Yang | 2020-01-28 |
| 10546955 | Dielectric isolated fin with improved fin profile | Bruce B. Doris, Darsen D. Lu, Ali Khakifirooz, Kern Rim | 2020-01-28 |
| 10546945 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Ruilong Xie, Steven R. Bentley, Nicolas Loubet, Pietro Montanini | 2020-01-28 |
| 10546942 | Nanosheet transistor with optimized junction and cladding defectivity control | Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2020-01-28 |
| 10546940 | On-chip integrated temperature protection device based on gel electrolyte | Qing Cao, Zhengwen Li, Fei Liu | 2020-01-28 |
| 10546857 | Vertical transistor transmission gate with adjacent NFET and PFET | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2020-01-28 |
| 10544042 | Nanoparticle structure and process for manufacture | Qing Cao, Juntao Li | 2020-01-28 |
| 10541128 | Method for making VFET devices with ILD protection | Zhenxing Bi, Juntao Li, Peng Xu | 2020-01-21 |
| 10541335 | Stress induction in 3D device channel using elastic relaxation of high stress material | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2020-01-21 |
| 10541330 | Forming stacked nanowire semiconductor device | Xin Miao, Peng Xu, Chen Zhang | 2020-01-21 |
| 10541312 | Air-gap top spacer and self-aligned metal gate for vertical fets | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2020-01-21 |
| 10541308 | Gate cut device fabrication with extended height gates | Andrew M. Greene, John R. Sporre, Peng Xu | 2020-01-21 |
| 10541253 | FinFETs with various fin height | Terence B. Hook, Xin Miao, Balasubramanian Pranatharthiharan | 2020-01-21 |
| 10541203 | Nickel-silicon fuse for FinFET structures | Keith E. Fogel, Pouya Hashemi, Alexander Reznicek | 2020-01-21 |
| 10541177 | Porous silicon relaxation medium for dislocation free CMOS devices | Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2020-01-21 |
| 10541176 | Vertical silicon/silicon-germanium transistors with multiple threshold voltages | Zhenxing Bi, Juntao Li, Peng Xu | 2020-01-21 |
| 10541172 | Semiconductor device with reduced contact resistance | Sean Teehan, Alex Varghese | 2020-01-21 |
| 10539528 | Stacked nanofluidics structure | — | 2020-01-21 |
| 10535733 | Method of forming a nanosheet transistor | Choonghyun Lee, Juntao Li, Peng Xu | 2020-01-14 |
| 10535567 | Methods and structures for forming uniform fins when using hardmask patterns | Peng Xu, Yann Mignot, Choonghyun Lee | 2020-01-14 |
| 10535755 | Closely packed vertical transistors with reduced contact resistance | Zhenxing Bi, Juntao Li, Peng Xu | 2020-01-14 |
| 10535754 | Method and structure for forming a vertical field-effect transistor | Peng Xu, Choonghyun Lee, Juntao Li | 2020-01-14 |