Issued Patents 2020
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10790191 | Selective removal process to create high aspect ratio fully self-aligned via | Amrita B. Mullick, Madhur Sachan, Swaminathan Srinivasan, Regina Freed, Uday Mitra | 2020-09-29 |
| 10727119 | Process integration approach of selective tungsten via fill | Feiyue Ma, Yu Lei, Kai Wu, Mehul Naik, Zhiyuan Wu +2 more | 2020-07-28 |
| 10707122 | Methods for depositing dielectric barrier layers and aluminum containing etch stop layers | Sree Rangasai V. Kesapragada, Kevin Moraes, Srinivas Guggilla, Mehul Naik, David Thompson +6 more | 2020-07-07 |
| 10692734 | Methods of patterning nickel silicide layers on a semiconductor device | Jong Mun Kim, Chentsau Chris Ying, Srinivas D. Nemani, Ellie Yieh | 2020-06-23 |
| 10692759 | Methods for manufacturing an interconnect structure for semiconductor devices | Hao Jiang, Hao Chen, Mehul Naik | 2020-06-23 |
| 10685849 | Damage free metal conductor formation | Jong Mun Kim, Maximillian Clemons, Minrui Yu, Mehul Naik, Chentsau Chris Ying | 2020-06-16 |
| 10651043 | Process integration method to tune resistivity of nickel silicide | Minrui Yu, Mehul Naik | 2020-05-12 |
| 10643895 | Self-aligned interconnects formed using subtractive techniques | Bencherki Mebarki, Huixiong Dai, Yongmei Chen, Mehul Naik | 2020-05-05 |
| 10636704 | Seam-healing method upon supra-atmospheric process in diffusion promoting ambient | Bencherki Mebarki, Sean S. Kang, Keith Tatseun Wong, Mehul Naik, Ellie Yieh +1 more | 2020-04-28 |
| 10546742 | Method to reduce trap-induced capacitance in interconnect dielectric barrier stack | Mehul Naik, Yong Cao, Yana Cheng, Weifeng YE | 2020-01-28 |