Issued Patents 2019
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10515906 | Forming large chips through stitching | Wen-Hsin Wei, Shang-Yun Hou, Weiming Chris Chen | 2019-12-24 |
| RE47709 | Forming grounded through-silicon vias in a semiconductor substrate | Chi-Chun Hsieh, Wei-Cheng Wu, Hsiao-Tsung Yen, Shang-Yun Hou, Shin-Puu Jeng | 2019-11-05 |
| 10319699 | Chip package having die structures of different heights | Wen-Hsin Wei, Chi-Hsi Wu, Chen-Hua Yu, Shang-Yun Hou, Weiming Chris Chen | 2019-06-11 |
| 10297550 | 3D IC architecture with interposer and interconnect structure for bonding dies | Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun-Ren Lai, Yung-Chi Lin | 2019-05-21 |
| 10269584 | 3D packages and methods for forming the same | Tzu-Wei Chiu, Cheng-Hsien Hsieh, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng | 2019-04-23 |
| 10262939 | Configurable routing for packaging applications | Chung-Yu Lu, Shin-Puu Jeng, Shang-Yun Hou, Tzuan-Horng Liu, Shih-Wen Huang +1 more | 2019-04-16 |
| 10175294 | Testing of semiconductor chips with microbumps | Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu, Chao-Hsiang Yang | 2019-01-08 |