Issued Patents 2018
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10096709 | Aspect ratio trapping (ART) for fabricating vertical semiconductor devices | Van H. Le, Benjamin Chu-Kung, Jack T. Kavalieros, Ravi Pillarisetty, Willy Rachmady +4 more | 2018-10-09 |
| 10096474 | Methods and structures to prevent sidewall defects during selective epitaxy | Niloy Mukherjee, Niti Goel, Sanaz K. Gardner, Pragyansri Pathi, Matthew V. Metz +6 more | 2018-10-09 |
| 10090405 | Semiconductor device having group III-V material active region and graded gate dielectric | Marko Radosavljevic, Ravi Pillarisetty, Matthew V. Metz | 2018-10-02 |
| 10084058 | Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains | Prashant Majhi, Mantu K. Hudait, Jack T. Kavalieros, Ravi Pillarisetty, Marko Radosavljevic +2 more | 2018-09-25 |
| 10084043 | High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin | Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani, Anand S. Murthy +4 more | 2018-09-25 |
| 10074718 | Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack | Marko Radosavljevic, Ravi Pillarisetty, Benjamin Chu-Kung, Niloy Mukherjee | 2018-09-11 |
| 10026845 | Deep gate-all-around semiconductor device having germanium or group III-V active layer | Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian +5 more | 2018-07-17 |
| 10020371 | Contact techniques and configurations for reducing parasitic resistance in nanowire transistors | Ravi Pillarisetty, Benjamin Chu-Kung, Willy Rachmady, Van H. Le, Niloy Mukherjee +3 more | 2018-07-10 |
| 9972686 | Germanium tin channel transistors | Ravi Pillarisetty, Van H. Le, Willy Rachmady, Roza Kotlyar, Marko Radosavljevic +4 more | 2018-05-15 |
| 9947780 | High electron mobility transistor (HEMT) and method of fabrication | Han Wui Then, Robert S. Chau, Benjamin Chu-Kung, Jack T. Kavalieros, Matthew V. Metz +3 more | 2018-04-17 |
| 9934976 | Methods of forming low interface resistance rare earth metal contacts and structures formed thereby | Niloy Mukherjee, Matt Metz, Jack T. Kavalieros, Robert S. Chau | 2018-04-03 |
| 9929273 | Apparatus and methods of forming fin structures with asymmetric profile | Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Nadia M. Rahhal-Orabi, Tahir Ghani +3 more | 2018-03-27 |
| 9911835 | Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs | Roza Kotlyar, Stephen M. Cea, Benjamin Chu-Kung, Uygar E. Avci, Rafael Rios +4 more | 2018-03-06 |
| 9905651 | GE and III-V channel semiconductor devices having maximized compliance and free surface relaxation | Ravi Pillarisetty, Sansaptak Dasgupta, Niti Goel, Van H. Le, Marko Radosavljevic +8 more | 2018-02-27 |
| 9899505 | Conductivity improvements for III-V semiconductor devices | Marko Radosavljevic, Prashant Majhi, Jack T. Kavalieros, Niti Goel, Wilman Tsai +3 more | 2018-02-20 |
| 9876014 | Germanium-based quantum well devices | Ravi Pillarisetty, Been-Yih Jin, Benjamin Chu-Kung, Matthew V. Metz, Jack T. Kavalieros +5 more | 2018-01-23 |
| 9871106 | Heterogeneous pocket for tunneling field effect transistors (TFETs) | Uygar E. Avci, Roza Kotlyar, Benjamin Chu-Kung, Ian A. Young | 2018-01-16 |
| 9865684 | Nanoscale structure with epitaxial film having a recessed bottom portion | Benjamin Chu-Kung, Van H. Le, Robert S. Chau, Sansaptak Dasgupta, Niti Goel +8 more | 2018-01-09 |