Issued Patents 2018
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10133667 | Efficient data storage and retrieval using a heterogeneous main memory | Tirthankar Lahiri, Juan R. Loaiza, Jesse Kamp, Prashant Gaharwar, Hariharan Lakshmanan +1 more | 2018-11-20 |
| 10120895 | Mirroring, in memory, data from disk to improve query performance | Jesse Kamp, Amit Ganesh, Vineet Marwah, Vivekanandhan Raja, Tirthankar Lahiri +6 more | 2018-11-06 |
| 10103263 | Strained channel region transistors employing source and drain stressors and systems including the same | Van H. Le, Harold W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros | 2018-10-16 |
| 10096709 | Aspect ratio trapping (ART) for fabricating vertical semiconductor devices | Van H. Le, Benjamin Chu-Kung, Gilbert Dewey, Jack T. Kavalieros, Ravi Pillarisetty +4 more | 2018-10-09 |
| 10096474 | Methods and structures to prevent sidewall defects during selective epitaxy | Niti Goel, Sanaz K. Gardner, Pragyansri Pathi, Matthew V. Metz, Sansaptak Dasgupta +6 more | 2018-10-09 |
| 10090461 | Oxide-based three-terminal resistive switching logic devices | Elijah V. Karpov, Prashant Majhi, Ravi Pillarisetty, Brian S. Doyle, Uday Shah +1 more | 2018-10-02 |
| 10074718 | Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack | Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Benjamin Chu-Kung | 2018-09-11 |
| 10050015 | Multi-device flexible electronics system on a chip (SOC) process integration | Ravi Pillarisetty, Sansaptak Dasgupta, Brian S. Doyle, Marko Radosavljevic, Han Wui Then | 2018-08-14 |
| 10025822 | Optimizing execution plans for in-memory-aware joins | Dinesh Das, Mohamed Zait, Jiaqi Yan | 2018-07-17 |
| 10026845 | Deep gate-all-around semiconductor device having germanium or group III-V active layer | Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian +5 more | 2018-07-17 |
| 10020371 | Contact techniques and configurations for reducing parasitic resistance in nanowire transistors | Ravi Pillarisetty, Benjamin Chu-Kung, Willy Rachmady, Van H. Le, Gilbert Dewey +3 more | 2018-07-10 |
| 10007691 | Prioritizing repopulation of in-memory compression units | Michael J. Gleeson, Jesse Kamp, Vineet Marwah, Tirthankar Lahiri, Juan R. Loaiza +4 more | 2018-06-26 |
| 10002148 | Memory-aware joins based in a database cluster | Mohamed Zait, Juan R. Loaiza, Vineet Marwah, Tirthankar Lahiri, Jiaqi Yan +1 more | 2018-06-19 |
| 9947780 | High electron mobility transistor (HEMT) and method of fabrication | Han Wui Then, Robert S. Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack T. Kavalieros +3 more | 2018-04-17 |
| 9934976 | Methods of forming low interface resistance rare earth metal contacts and structures formed thereby | Matt Metz, Gilbert Dewey, Jack T. Kavalieros, Robert S. Chau | 2018-04-03 |
| 9923087 | Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation | Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Niti Goel, Sanaz K. Gardner +3 more | 2018-03-20 |
| 9905651 | GE and III-V channel semiconductor devices having maximized compliance and free surface relaxation | Ravi Pillarisetty, Sansaptak Dasgupta, Niti Goel, Van H. Le, Marko Radosavljevic +8 more | 2018-02-27 |
| 9899505 | Conductivity improvements for III-V semiconductor devices | Marko Radosavljevic, Prashant Majhi, Jack T. Kavalieros, Niti Goel, Wilman Tsai +3 more | 2018-02-20 |
| 9881048 | Mirroring, in memory, data from disk to improve query performance | Jesse Kamp, Amit Ganesh, Vineet Marwah, Vivekanandhan Raja, Tirthankar Lahiri +6 more | 2018-01-30 |
| 9876014 | Germanium-based quantum well devices | Ravi Pillarisetty, Been-Yih Jin, Benjamin Chu-Kung, Matthew V. Metz, Jack T. Kavalieros +5 more | 2018-01-23 |
| 9875259 | Distribution of an object in volatile memory across a multi-node cluster | Tirthankar Lahiri, Vineet Marwah, Kartik Kulkarni | 2018-01-23 |
| 9865684 | Nanoscale structure with epitaxial film having a recessed bottom portion | Benjamin Chu-Kung, Van H. Le, Robert S. Chau, Sansaptak Dasgupta, Gilbert Dewey +8 more | 2018-01-09 |
| 9859278 | Bi-axial tensile strained GE channel for CMOS | Prashant Majhi, Ravi Pillarisetty, Willy Rachmady, Robert S. Chau | 2018-01-02 |