SS

Seung Hoon Sung

IN Intel: 10 patents #145 of 5,158Top 3%
Overall (2018): #6,224 of 503,207Top 2%
10
Patents 2018

Issued Patents 2018

Patent #TitleCo-InventorsDate
10121861 Nanowire transistor fabrication with hardmask layers Seiyon Kim, Kelin J. Kuhn, Willy Rachmady, Jack T. Kavalieros 2018-11-06
10096474 Methods and structures to prevent sidewall defects during selective epitaxy Niloy Mukherjee, Niti Goel, Sanaz K. Gardner, Pragyansri Pathi, Matthew V. Metz +6 more 2018-10-09
10096683 Group III-N transistor on nanoscale template structures Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Benjamin Chu-Kung, Sanaz K. Gardner +1 more 2018-10-09
10096682 III-N devices in Si trenches Sansaptak Dasgupta, Han Wui Then, Sanaz K. Gardner, Marko Radosavljevic, Benjamin Chu-Kung +3 more 2018-10-09
10056456 N-channel gallium nitride transistors Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Sanaz K. Gardner, Robert S. Chau 2018-08-21
10038054 Variable gate width for gate all-around transistors Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jack T. Kavalieros, Robert S. Chau 2018-07-31
10032911 Wide band gap transistor on non-native semiconductor substrate Han Wui Then, Robert S. Chau, Sansaptak Dasgupta, Marko Radosavljevic, Benjamin Chu-Kung +2 more 2018-07-24
10026845 Deep gate-all-around semiconductor device having germanium or group III-V active layer Ravi Pillarisetty, Willy Rachmady, Van H. Le, Jessica S. Kachian, Jack T. Kavalieros +5 more 2018-07-17
9922826 Integrated circuit die having reduced defect group III-nitride layer and methods associated therewith Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Robert S. Chau, Sanaz K. Gardner 2018-03-20
9923087 Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Niloy Mukherjee, Niti Goel +3 more 2018-03-20