Issued Patents 2018
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10096474 | Methods and structures to prevent sidewall defects during selective epitaxy | Niloy Mukherjee, Niti Goel, Pragyansri Pathi, Matthew V. Metz, Sansaptak Dasgupta +6 more | 2018-10-09 |
| 10096683 | Group III-N transistor on nanoscale template structures | Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Benjamin Chu-Kung, Seung Hoon Sung +1 more | 2018-10-09 |
| 10096682 | III-N devices in Si trenches | Sansaptak Dasgupta, Han Wui Then, Seung Hoon Sung, Marko Radosavljevic, Benjamin Chu-Kung +3 more | 2018-10-09 |
| 10084043 | High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin | Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani +4 more | 2018-09-25 |
| 10056456 | N-channel gallium nitride transistors | Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Seung Hoon Sung, Robert S. Chau | 2018-08-21 |
| 10032911 | Wide band gap transistor on non-native semiconductor substrate | Han Wui Then, Robert S. Chau, Sansaptak Dasgupta, Marko Radosavljevic, Benjamin Chu-Kung +2 more | 2018-07-24 |
| 9922826 | Integrated circuit die having reduced defect group III-nitride layer and methods associated therewith | Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Robert S. Chau, Seung Hoon Sung | 2018-03-20 |
| 9923087 | Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation | Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Niloy Mukherjee, Niti Goel +3 more | 2018-03-20 |