Issued Patents 2018
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10153372 | High mobility strained channels for fin-based NMOS transistors | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy +1 more | 2018-12-11 |
| 10147817 | Techniques for integration of Ge-rich p-MOS source/drain | Glenn A. Glass, Anand S. Murthy, Ying-Feng PANG, Nabil G. Mistkawi | 2018-12-04 |
| 10141226 | Self-aligned contacts | Mark Bohr, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus +2 more | 2018-11-27 |
| 10121856 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Kelin J. Kuhn, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2018-11-06 |
| 10109711 | CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channel | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass +1 more | 2018-10-23 |
| 10084043 | High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin | Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Anand S. Murthy +4 more | 2018-09-25 |
| 10074573 | CMOS nanowire structure | Seiyon Kim, Kelin J. Kuhn, Anand S. Murthy, Annalisa Cappellani, Stephen M. Cea +2 more | 2018-09-11 |
| 10056380 | Non-planar semiconductor device having doped sub-fin region and method to fabricate same | Salman Latif, Chanaka D. Munasinghe | 2018-08-21 |
| 10026829 | Semiconductor device with isolated body portion | Annalisa Cappellani, Stephen M. Cea, Harry Gomez, Jack T. Kavalieros, Patrick H. Keys +5 more | 2018-07-17 |
| 9997563 | Logic chip including embedded magnetic tunnel junctions | Kevin J. Lee, Joseph M. Steigerwald, John H. Epple, Yih Wang | 2018-06-12 |
| 9935107 | CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the same | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Kelin J. Kuhn | 2018-04-03 |
| 9929273 | Apparatus and methods of forming fin structures with asymmetric profile | Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey, Nadia M. Rahhal-Orabi +3 more | 2018-03-27 |
| 9923054 | Fin structure having hard mask etch stop layers underneath gate sidewall spacers | Ritesh Jhaveri, Bernard Sell | 2018-03-20 |
| 9893149 | High mobility strained channels for fin-based transistors | Stephen M. Cea, Anand S. Murthy, Glenn A. Glass, Daniel B. Aubertine, Jack T. Kavalieros +1 more | 2018-02-13 |
| 9892967 | Self-aligned contacts | Mark Bohr, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus +2 more | 2018-02-13 |
| 9882027 | Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions | Szuya S. Liao, Michael L. Hattendorf | 2018-01-30 |
| 9876016 | Wrap-around trench contact structure and methods of fabrication | Joseph M. Steigerwald, Oleg Golonzka | 2018-01-23 |
| 9859424 | Techniques for integration of Ge-rich p-MOS source/drain contacts | Glenn A. Glass, Anand S. Murthy, Ying-Feng PANG, Nabil G. Mistkawi | 2018-01-02 |
| 9859368 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Kelin J. Kuhn, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2018-01-02 |