Issued Patents 2018
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10153372 | High mobility strained channels for fin-based NMOS transistors | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Willy Rachmady +1 more | 2018-12-11 |
| 10147817 | Techniques for integration of Ge-rich p-MOS source/drain | Anand S. Murthy, Tahir Ghani, Ying-Feng PANG, Nabil G. Mistkawi | 2018-12-04 |
| 10141311 | Techniques for achieving multiple transistor fin dimensions on a single die | Anand S. Murthy | 2018-11-27 |
| 10109711 | CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channel | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Kelin J. Kuhn +1 more | 2018-10-23 |
| 10109628 | Transistor device with gate control layer undercutting the gate dielectric | Anand S. Murthy, Nick Lindert | 2018-10-23 |
| 10090383 | Column IV transistors for PMOS integration | Anand S. Murthy | 2018-10-02 |
| 10084043 | High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin | Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani +4 more | 2018-09-25 |
| 10074573 | CMOS nanowire structure | Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Annalisa Cappellani +2 more | 2018-09-11 |
| 10014412 | Pre-sculpting of Si fin elements prior to cladding for transistor channel applications | Anand S. Murthy, Daniel B. Aubertine, Subhash M. Joshi | 2018-07-03 |
| 9997414 | Ge/SiGe-channel and III-V-channel transistors on the same die | Anand S. Murthy, Karthik Jambunathan | 2018-06-12 |
| 9966440 | Tin doped III-V material contacts | Anand S. Murthy, Michael Jackson, Harold W. Kennel | 2018-05-08 |
| 9929273 | Apparatus and methods of forming fin structures with asymmetric profile | Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey, Nadia M. Rahhal-Orabi +3 more | 2018-03-27 |
| 9893149 | High mobility strained channels for fin-based transistors | Stephen M. Cea, Anand S. Murthy, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros +1 more | 2018-02-13 |
| 9882009 | High resistance layer for III-V channel deposited on group IV substrates for MOS transistors | Anand S. Murthy | 2018-01-30 |
| 9876113 | Method for improving transistor performance through reducing the salicide interface resistance | Anand S. Murthy, Boyan Boyanov, Thomas Hoffmann | 2018-01-23 |
| 9859424 | Techniques for integration of Ge-rich p-MOS source/drain contacts | Anand S. Murthy, Tahir Ghani, Ying-Feng PANG, Nabil G. Mistkawi | 2018-01-02 |