{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "2018", "item": "https://www.patentleaderboard.com/2018/"}, {"@type": "ListItem", "position": 3, "name": "Intel", "item": "https://www.patentleaderboard.com/2018/company/intel"}, {"@type": "ListItem", "position": 4, "name": "Daniel B. Aubertine", "item": "https://www.patentleaderboard.com/2018/inventor/fl:da_ln:aubertine-3"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
DA

Daniel B. Aubertine — 2 Patents in 2018

Intel: 2 patents #1,186 of 5,158Top 25%
North Plains, OR: #10 of 28 inventorsTop 40%
Oregon: #985 of 4,132 inventorsTop 25%
Overall (2018): #157,273 of 503,207Top 35%
2 Patents 2018

Issued Patents 2018

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10084087 Enhanced dislocation stress transistor Cory E. Weber, Mark Liu, Anand S. Murthy, Hemant Deshpande 2018-09-25 $26,257,000
10014412 Pre-sculpting of Si fin elements prior to cladding for transistor channel applications Glenn A. Glass, Anand S. Murthy, Subhash M. Joshi 2018-07-03 $24,450,000