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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Anand S. Murthy — 19 Patents in 2018

Intel: 19 patents #47 of 5,158Top 1%
Portland, OR: #17 of 1,708 inventorsTop 1%
Oregon: #25 of 4,132 inventorsTop 1%
Overall (2018): #1,737 of 503,207Top 1%
19 Patents 2018

Issued Patents 2018

Showing 1–19 of 19 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10153372 High mobility strained channels for fin-based NMOS transistors Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Willy Rachmady +1 more 2018-12-11 $24,515,000
10147817 Techniques for integration of Ge-rich p-MOS source/drain Glenn A. Glass, Tahir Ghani, Ying-Feng PANG, Nabil G. Mistkawi 2018-12-04 $23,085,000
10141311 Techniques for achieving multiple transistor fin dimensions on a single die Glenn A. Glass 2018-11-27 $28,030,000
10121856 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Mark Armstrong, Rafael Rios +2 more 2018-11-06 $18,970,000
10109711 CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channel Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Kelin J. Kuhn +1 more 2018-10-23 $21,867,000
10109628 Transistor device with gate control layer undercutting the gate dielectric Nick Lindert, Glenn A. Glass 2018-10-23 $21,867,000
10090383 Column IV transistors for PMOS integration Glenn A. Glass 2018-10-02 $23,827,000
10084087 Enhanced dislocation stress transistor Cory E. Weber, Mark Liu, Hemant Deshpande, Daniel B. Aubertine 2018-09-25 $26,257,000
10084043 High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani +4 more 2018-09-25 $26,257,000
10074573 CMOS nanowire structure Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Annalisa Cappellani, Stephen M. Cea +2 more 2018-09-11 $19,778,000
10014412 Pre-sculpting of Si fin elements prior to cladding for transistor channel applications Glenn A. Glass, Daniel B. Aubertine, Subhash M. Joshi 2018-07-03 $24,450,000
9997414 Ge/SiGe-channel and III-V-channel transistors on the same die Glenn A. Glass, Karthik Jambunathan 2018-06-12 $21,622,000
9966440 Tin doped III-V material contacts Glenn A. Glass, Michael Jackson, Harold W. Kennel 2018-05-08 $30,284,000
9929273 Apparatus and methods of forming fin structures with asymmetric profile Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey, Nadia M. Rahhal-Orabi +3 more 2018-03-27 $21,620,000
9893149 High mobility strained channels for fin-based transistors Stephen M. Cea, Glenn A. Glass, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros +1 more 2018-02-13 $15,494,000
9882009 High resistance layer for III-V channel deposited on group IV substrates for MOS transistors Glenn A. Glass 2018-01-30 $22,157,000
9876113 Method for improving transistor performance through reducing the salicide interface resistance Boyan Boyanov, Glenn A. Glass, Thomas Hoffmann 2018-01-23 $21,180,000
9859424 Techniques for integration of Ge-rich p-MOS source/drain contacts Glenn A. Glass, Tahir Ghani, Ying-Feng PANG, Nabil G. Mistkawi 2018-01-02 $11,729,000
9859368 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Mark Armstrong, Rafael Rios +2 more 2018-01-02 $11,729,000