SC

Stephen M. Cea

IN Intel: 9 patents #168 of 5,158Top 4%
Overall (2018): #7,643 of 503,207Top 2%
9
Patents 2018

Issued Patents 2018

Patent #TitleCo-InventorsDate
10153372 High mobility strained channels for fin-based NMOS transistors Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy, Willy Rachmady +1 more 2018-12-11
10109711 CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channel Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn +1 more 2018-10-23
10074573 CMOS nanowire structure Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Annalisa Cappellani +2 more 2018-09-11
10026829 Semiconductor device with isolated body portion Annalisa Cappellani, Tahir Ghani, Harry Gomez, Jack T. Kavalieros, Patrick H. Keys +5 more 2018-07-17
9935107 CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the same Roza Kotlyar, Harold W. Kennel, Kelin J. Kuhn, Tahir Ghani 2018-04-03
9911835 Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs Roza Kotlyar, Gilbert Dewey, Benjamin Chu-Kung, Uygar E. Avci, Rafael Rios +4 more 2018-03-06
9905651 GE and III-V channel semiconductor devices having maximized compliance and free surface relaxation Ravi Pillarisetty, Sansaptak Dasgupta, Niti Goel, Van H. Le, Marko Radosavljevic +8 more 2018-02-27
9905650 Uniaxially strained nanowire structure Seiyon Kim, Annalisa Cappellani 2018-02-27
9893149 High mobility strained channels for fin-based transistors Anand S. Murthy, Glenn A. Glass, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros +1 more 2018-02-13