Issued Patents 2018
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10145694 | Technologies for providing information to a user while traveling | Ren Wang, Zhonghong Ou, Kristoffer Fleming, Tsung-Yuan C. Tai, Timothy J. Gresham +2 more | 2018-12-04 |
| 10147676 | Wafer-scale power delivery | Charles E. Cox, Harald Huels, Xiao Hu Liu, Ahmet S. Ozcan, Winfried W. Wilcke | 2018-12-04 |
| 10133396 | Virtual input device using second touch-enabled display | John J. Valavi, Murali Ramadoss | 2018-11-20 |
| 10049942 | Asymmetric semiconductor device and method of forming same | Anthony I. Chou, Judson R. Holt, Henry K. Utomo | 2018-08-14 |
| 10032862 | Semiconductor structure with integrated passive structures | Anthony I. Chou, Renee T. Mo, Shreesh Narasimha | 2018-07-24 |
| 10025981 | Visual object and event detection and prediction system using saccades | Ban Kawas, Janusz Marecki, Sharathchandra U. Pankanti | 2018-07-17 |
| D822658 | Computer notebook | Jim Okuley, Murali Veeramoney, Prosenjit Ghosh, Denica N. Larsen, Martin Bone +2 more | 2018-07-10 |
| 10002900 | Three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes | Mark C. H. Lamorey | 2018-06-19 |
| 10002876 | FinFET vertical flash memory | Ramachandra Divakaruni, Carl Radens | 2018-06-19 |
| 9991167 | Method and IC structure for increasing pitch between gates | Murshed Chowdhury, Brian J. Greene, Chung-Hsun Lin | 2018-06-05 |
| 9934138 | Application testing on a blockchain | Vijay Kumar Ananthapur Bache, Jhilam Bera, Bidhu Ranjan Sahoo | 2018-04-03 |
| 9923082 | Junction butting structure using nonuniform trench shape | Anthony I. Chou, Judson R. Holt, Henry K. Utomo | 2018-03-20 |
| 9922831 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2018-03-20 |
| 9904341 | Cascading power consumption | Brian E. Woodruff, David M. Putzolu, Mark R. Walker | 2018-02-27 |
| 9892086 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Rahul C. Shah | 2018-02-13 |
| 9886193 | Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration | Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Winfried W. Wilcke | 2018-02-06 |
| 9881956 | Heterogeneous integration using wafer-to-wafer stacking with die size adjustment | Mark C. H. Lamorey | 2018-01-30 |
| 9870503 | Visual object and event detection and prediction system using saccades | Ban Kawas, Janusz Marecki, Sharathchandra U. Pankanti | 2018-01-16 |
| 9859122 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2018-01-02 |