Issued Patents 2018
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10083880 | Hybrid ETSOI structure to minimize noise coupling from TSV | Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman | 2018-09-25 |
| 10056487 | Strained semiconductor nanowire | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2018-08-21 |
| 10014214 | Electronic device including moat power metallization in trench | Josephine B. Chang, Leland Chang, Michael A. Guillorn, Adam M. Pyzyna | 2018-07-03 |
| 9991167 | Method and IC structure for increasing pitch between gates | Arvind Kumar, Murshed Chowdhury, Brian J. Greene | 2018-06-05 |
| 9922831 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2018-03-20 |
| 9899525 | Increased contact area for finFETs | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh | 2018-02-20 |
| 9859122 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2018-01-02 |