Issued Patents 2018
Showing 26–50 of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10002939 | Nanosheet transistors having thin and thick gate dielectric material | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2018-06-19 |
| 10002945 | Composite spacer enabling uniform doping in recessed fin devices | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2018-06-19 |
| 10002921 | Nanowire semiconductor device including lateral-etch barrier region | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2018-06-19 |
| 9997609 | Implantation formed metal-insulator-semiconductor (MIS) contacts | Chia-Yu Chen, Zuoguang Liu, Tenko Yamashita | 2018-06-12 |
| 9997367 | Non-lithographic line pattern formation | Chiahsun Tseng, David V. Horak, Yunpeng Yin | 2018-06-12 |
| 9997418 | Dual liner silicide | Balasubramanian Pranatharthiharan, Ruilong Xie | 2018-06-12 |
| 9991355 | Implantation formed metal-insulator-semiconductor (MIS) contacts | Chia-Yu Chen, Zuoguang Liu, Tenko Yamashita | 2018-06-05 |
| 9991255 | FinFETs with non-merged epitaxial S/D extensions on a seed layer and having flat top surfaces | Hong He, Shogo Mochizuki, Chiahsun Tseng, Yunpeng Yin | 2018-06-05 |
| 9991258 | FinFETs with non-merged epitaxial S/D extensions having a SiGe seed layer on insulator | Hong He, Shogo Mochizuki, Chiahsun Tseng, Yunpeng Yin | 2018-06-05 |
| 9991366 | Anchored stress-generating active semiconductor regions for semiconductor-on-insulator FinFET | Veeraraghavan S. Basker, Krishna Iyengar, Tenko Yamashita | 2018-06-05 |
| 9985130 | Salicide formation on replacement metal gate finFET devices | Effendi Leobandung, Soon-Cheon Seo, Tenko Yamashita | 2018-05-29 |
| 9985096 | High thermal budget compatible punch through stop integration using doped glass | Kangguo Cheng, Sanjay C. Mehta, Xin Miao | 2018-05-29 |
| 9985030 | FinFET semiconductor device having integrated SiGe fin | Kangguo Cheng, Hong He, Ali Khakifirooz, Chiahsun Tseng, Yunpeng Yin | 2018-05-29 |
| 9972682 | Low resistance source drain contact formation | Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi | 2018-05-15 |
| 9960271 | Method of forming vertical field effect transistors with different threshold voltages and the resulting integrated circuit structure | Ruilong Xie, Tenko Yamashita, Kangguo Cheng | 2018-05-01 |
| 9953977 | FinFET semiconductor device | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2018-04-24 |
| 9947744 | Nanowire semiconductor device including lateral-etch barrier region | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2018-04-17 |
| 9947791 | FinFET with merge-free fins | Hong He, Chiahsun Tseng, Junli Wang, Yunpeg Yin | 2018-04-17 |
| 9947586 | Tunneling fin type field effect transistor with epitaxial source and drain regions | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2018-04-17 |
| 9935179 | Method for making semiconductor device with filled gate line end recesses | Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie | 2018-04-03 |
| 9935201 | High doped III-V source/drain junctions for field effect transistors | Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie | 2018-04-03 |
| 9935018 | Methods of forming vertical transistor devices with different effective gate lengths | Ruilong Xie, Tenko Yamashita, Kangguo Cheng | 2018-04-03 |
| 9929246 | Forming air-gap spacer for vertical field effect transistor | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2018-03-27 |
| 9929253 | Method for making a semiconductor device with sidewal spacers for confinig epitaxial growth | Xiuyu Cai, Qing Liu, Ruilong Xie | 2018-03-27 |
| 9929059 | Dual liner silicide | Balasubramanian Pranatharthiharan, Ruilong Xie | 2018-03-27 |