Issued Patents 2017
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9842816 | Conductive pad structure for hybrid bonding and methods of forming same | Sheng-Chau Chen, Shih Pei Chou, Yen-Chang Chu, Cheng-Hsien Chou, Chih-Hui Huang | 2017-12-12 |
| 9837291 | Wafer processing method and apparatus | Chih-Hui Huang, Chun-Han Tsao, Sheng-Chau Chen, Chia-Shiung Tsai, Xiaomeng Chen | 2017-12-05 |
| 9831328 | Bipolar junction transistor (BJT) base conductor pullback | Lih-Tien Shyu | 2017-11-28 |
| 9812477 | Photodiode gate dielectric protection layer | Cheng-Hsien Chou, Wen-I Hsu, Tsun-Kai Tsao, Chih-Yu Lai, Jiech-Fun Lu | 2017-11-07 |
| 9799702 | Deep trench isolation structure and method of forming same | Yu-Hung Cheng, Tung-I Lin, Cheng-Lung Wu, Wei-Li Chen | 2017-10-24 |
| 9793243 | Buffer layer(s) on a stacked structure having a via | Chen-Fa Lu, Cheng-Yuan Tsai, Chia-Shiung Tsai | 2017-10-17 |
| 9786619 | Semiconductor structure and manufacturing method thereof | Sheng-Chau Chen, Shih Pei Chou, Ming-Jhe Lee, Kuo-Ming Wu, Cheng-Hsien Chou +1 more | 2017-10-10 |
| 9754813 | Bond chuck, methods of bonding, and tool including bond chuck | Chih-Hui Huang, Yen-Chang Chu, Kuan-Liang Liu, Ping-Yin Liu, Cheng-Yuan Tsai +2 more | 2017-09-05 |
| 9711555 | Dual facing BSI image sensors with wafer level stacking | Ping-Yin Liu, Chia-Shiung Tsai, Xiaomeng Chen, Pin-Nan Tseng | 2017-07-18 |
| 9704904 | Deep trench isolation structures and methods of forming same | Chih-Yu Lai, Cheng-Hsien Chou, Cheng-Yuan Tsai, Yen-Ting Chiang | 2017-07-11 |
| 9679980 | Common source oxide formation by in-situ steam oxidation for embedded flash | Yu-Hung Cheng, Cheng-Ta Wu, Chia-Shiung Tsai, Ru-Liang Lee, I-Ting Li +1 more | 2017-06-13 |
| 9673239 | Image sensor device and method | Yen-Chang Chu, Cheng-Yuan Tsai | 2017-06-06 |
| 9659981 | Backside illuminated image sensor with negatively charged layer | Shyh-Fann Ting, Chih-Yu Lai, Cheng-Ta Wu, Ching-Chun Wang | 2017-05-23 |
| 9653507 | Deep trench isolation shrinkage method for enhanced device performance | Cheng-Hsien Chou, Shih Pei Chou, Chih-Yu Lai, Sheng-Chau Chen, Chih-Ta Chen +1 more | 2017-05-16 |
| 9634096 | Semiconductor device with trench isolation | Yu-Hung Cheng, Cheng-Ta Wu, Chia-Shiung Tsai, Ru-Liang Lee, Tung-I Lin +1 more | 2017-04-25 |
| 9627243 | Method and apparatus of holding a device | Ping-Yin Liu, Chung-Yi Yu, Che Ying Hsu, Da-Hsiang Chou, Chia-Shiung Tsai | 2017-04-18 |
| 9627326 | Method for forming alignment marks and structure of same | Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai +7 more | 2017-04-18 |
| 9595589 | Transistor with performance boost by epitaxial layer | Yu-Hung Cheng, Cheng-Ta Wu, Chia-Shiung Tsai, Ru-Liang Lee, Tung-I Lin +1 more | 2017-03-14 |
| 9576827 | Apparatus and method for wafer level bonding | Ping-Yin Liu, Yen-Chang Chu, Xin-Hua Huang, Lan-Lin Chao, Ru-Liang Lee | 2017-02-21 |
| 9570431 | Semiconductor wafer for integrated packages | Cheng-Te Lee, Chung-Yi Yu, Jen-Cheng Liu, Kuan-Chieh Huang | 2017-02-14 |