Issued Patents 2017
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9818858 | Multi-layer active layer having a partial recess | Chi-Ming Chen, Kuei-Ming Chen | 2017-11-14 |
| 9741800 | III-V multi-channel FinFETs | Hung-Ta Lin, Chun-Feng Nieh, Chi-Ming Chen | 2017-08-22 |
| 9685518 | Method of forming semiconductor structure of control gate, and semiconductor device | Chih-Ming Chen, Chin-Cheng Chang, Szu-Yu Wang, Chia-Shiung Tsai, Ru-Liang Lee | 2017-06-20 |
| 9660063 | Semiconductor structure having sets of III-V compound layers and method of forming the same | Chi-Ming Chen, Po-Chun Liu, Chia-Shiung Tsai | 2017-05-23 |
| 9646938 | Integrated circuit with backside structures to reduce substrate warp | Chih-Ming Chen, Szu-Yu Wang | 2017-05-09 |
| 9634105 | Silicon nano-tip thin film for flash memory cells | Tsu-Hui Su, Chih-Ming Chen, Chia-Shiung Tsai, Szu-Yu Wang | 2017-04-25 |
| 9627243 | Method and apparatus of holding a device | Ping-Yin Liu, Che Ying Hsu, Yeur-Luen Tu, Da-Hsiang Chou, Chia-Shiung Tsai | 2017-04-18 |
| 9620362 | Seed layer structure for growth of III-V materials on silicon | Chi-Ming Chen, Po-Chun Liu | 2017-04-11 |
| 9577077 | Well controlled conductive dot size in flash memory | Tsu-Hui Su, Chih-Ming Chen, Szu-Yu Wang, Chia-Shiung Tsai | 2017-02-21 |
| 9570431 | Semiconductor wafer for integrated packages | Cheng-Te Lee, Jen-Cheng Liu, Kuan-Chieh Huang, Yeur-Luen Tu | 2017-02-14 |
| 9548376 | Method of manufacturing a semiconductor device including a barrier structure | Po-Chun Liu, Chi-Ming Chen, Chen-Hao Chiang, Chia-Shiung Tsai, Xiaomeng Chen | 2017-01-17 |