Issued Patents 2017
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9711604 | Loading effect reduction through multiple coat-etch processes | Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Stan Chen | 2017-07-18 |
| 9660063 | Semiconductor structure having sets of III-V compound layers and method of forming the same | Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai | 2017-05-23 |
| 9620362 | Seed layer structure for growth of III-V materials on silicon | Chi-Ming Chen, Chung-Yi Yu | 2017-04-11 |
| 9548376 | Method of manufacturing a semiconductor device including a barrier structure | Chi-Ming Chen, Chen-Hao Chiang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen | 2017-01-17 |