Issued Patents 2017
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9842816 | Conductive pad structure for hybrid bonding and methods of forming same | Shih Pei Chou, Yen-Chang Chu, Cheng-Hsien Chou, Chih-Hui Huang, Yeur-Luen Tu | 2017-12-12 |
| 9837291 | Wafer processing method and apparatus | Chih-Hui Huang, Chun-Han Tsao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen | 2017-12-05 |
| 9786619 | Semiconductor structure and manufacturing method thereof | Shih Pei Chou, Ming-Jhe Lee, Kuo-Ming Wu, Cheng-Hsien Chou, Cheng-Yuan Tsai +1 more | 2017-10-10 |
| 9704827 | Hybrid bond pad structure | Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung +1 more | 2017-07-11 |
| 9666566 | 3DIC structure and method for hybrid bonding semiconductor wafers | Ju-Shi Chen, Cheng-Ying Ho, Chun-Chieh Chuang, Shih Pei Chou, Hui-Wen Shen +4 more | 2017-05-30 |
| 9653507 | Deep trench isolation shrinkage method for enhanced device performance | Cheng-Hsien Chou, Shih Pei Chou, Chih-Yu Lai, Chih-Ta Chen, Yeur-Luen Tu +1 more | 2017-05-16 |
| 9627326 | Method for forming alignment marks and structure of same | Cheng-Hsien Chou, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu +7 more | 2017-04-18 |