Issued Patents 2016
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9502350 | Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer and forming second conductive material on dielectric layer | Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon | 2016-11-22 |
| 9472477 | Electromigration test structure for Cu barrier integrity and blech effect evaluations | Griselda Bonilla, Chao-Kun Hu, Baozhen Li, Paul S. McLaughlin | 2016-10-18 |
| 9431292 | Alternate dual damascene method for forming interconnects | Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon | 2016-08-30 |
| 9379057 | Method and structure to reduce the electric field in semiconductor wiring interconnects | Takeshi Nogami, Raghuveer R. Patlolla, Christopher J. Penny, Theodorus E. Standaert | 2016-06-28 |
| 9349687 | Advanced manganese/manganese nitride cap/etch mask for air gap formation scheme in nanocopper low-K interconnect | Stephen M. Gates, Joe Lee, Son V. Nguyen, Brown C. Peethala, Christopher J. Penny +1 more | 2016-05-24 |
| 9332628 | Microelectronic structure including air gap | Daniel C. Edelstein, David V. Horak, Satyanarayana V. Nitta, Takeshi Nogami, Shom Ponoth +1 more | 2016-05-03 |
| 9324650 | Interconnect structures with fully aligned vias | Daniel C. Edelstein, Nicholas C. M. Fuller, Satyanarayana V. Nitta, David L. Rath | 2016-04-26 |
| 9305836 | Air gap semiconductor structure with selective cap bilayer | Stephen M. Gates, Dimitri Kioussis, Christopher J. Penny, Deepika Priyadarshini | 2016-04-05 |