JD

Javier A. Delacruz

XC Xcelsis: 36 patents #1 of 19Top 6%
IN Invensas: 34 patents #12 of 142Top 9%
AT Adeia Semiconductor Bonding Technologies: 29 patents #7 of 46Top 20%
IT Invensas Bonding Technologies: 22 patents #4 of 21Top 20%
AS Adeia Semiconductor: 15 patents #1 of 14Top 8%
ES Esilicon: 6 patents #3 of 22Top 15%
W& Whitaker &: 1 patents #650 of 1,437Top 50%
📍 San Jose, CA: #115 of 32,062 inventorsTop 1%
🗺 California: #1,075 of 386,348 inventorsTop 1%
Overall (All Time): #6,832 of 4,157,543Top 1%
143
Patents All Time

Issued Patents All Time

Showing 76–100 of 143 patents

Patent #TitleCo-InventorsDate
10978348 3D chip sharing power interconnect layer Steven Teig, Ilyas Mohammed 2021-04-13
10970627 Time borrowing between layers of a three dimensional chip stack Steven Teig, Kenneth Duong 2021-04-06
10950547 Stacked IC structure with system level wiring on multiple sides of the IC die Ilyas Mohammed, Steven Teig 2021-03-16
10923408 Cavity packages Shaowu Huang, Liang Wang, Rajesh Katkar, Belgacem Haba 2021-02-16
10923413 Hard IP blocks with physically bidirectional passageways 2021-02-16
10910344 Systems and methods for releveled bump planes for chiplets Belgacem Haba, Cyprian Emeka Uzoh, Rajesh Katkar, Ilyas Mohammed 2021-02-02
10892252 Face-to-face mounted IC dies with orthogonal top interconnect layers Eric Nequist, Steven Teig, Ilyas Mohammed, Laura Mirkarimi 2021-01-12
10886177 3D chip with shared clock distribution network Steven Teig, Ilyas Mohammed 2021-01-05
10879207 Bonded structures Liang Wang, Rajesh Katkar, Arkalgud R. Sitaram 2020-12-29
10879210 Bonded structures Paul M. Enquist, Liang Wang, Rajesh Katkar, Arkalgud R. Sitaram 2020-12-29
10832912 Direct-bonded native interconnects and active base die Steven Teig, Shaowu Huang, William C. Plants, David Edward Fisch 2020-11-10
10790222 Bonding of laminates with electrical interconnects Belgacem Haba, Wael Zohni, Liang Wang, Akash Agrawal 2020-09-29
10784191 Interface structures and methods for forming same Shaowu Huang, Belgacem Haba 2020-09-22
10748824 Probe methodology for ultrafine pitch interconnects Paul M. Enquist, Gaius Gillman Fountain, Jr., Ilyas Mohammed 2020-08-18
10719762 Three dimensional chip structure implementing machine trained network Steven Teig, Kenneth Duong 2020-07-21
10700094 Device disaggregation for improved performance Don Draper, Jung Ko, Steven Teig 2020-06-30
10684929 Self healing compute array Steven Teig, David Edward Fisch, William C. Plants 2020-06-16
10672744 3D compute circuit with high density Z-axis interconnects Steven Teig, Ilyas Mohammed, Kenneth Duong 2020-06-02
10672663 3D chip sharing power circuit Steven Teig, Ilyas Mohammed, Eric Nequist 2020-06-02
10672745 3D processor Steven Teig, Ilyas Mohammed, Kenneth Duong 2020-06-02
10672743 3D Compute circuit with high density z-axis interconnects Steven Teig, Ilyas Mohammed, Kenneth Duong 2020-06-02
10664564 Systems and methods for inter-die block level design Eric Nequist, Jung Ko, Kenneth Duong 2020-05-26
10658302 Wire bonding method and apparatus for electromagnetic interference shielding Shaowu Huang 2020-05-19
10658313 Selective recess Rajesh Katkar, Shaowu Huang, Gaius Gillman Fountain, Jr., Liang Wang, Laura Wills Mirkarimi 2020-05-19
10607136 Time borrowing between layers of a three dimensional chip stack Steven Teig, Kenneth Duong 2020-03-31