Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9418872 | Packaged microelectronic components | Meow Koon Eng, Sui Waf Low, Yong Poo Chia, Bok Leng Ser, Wei Zhou | 2016-08-16 |
| 6882021 | Packaged image sensing microelectronic devices including a lead and methods of packaging image sensing microelectronic devices including a lead | Suan Jeung Boon, Yong Poo Chia, Meow Koon Eng, Siu Waf Low, Swee Kwang Chua | 2005-04-19 |
| 6468831 | Method of fabricating thin integrated circuit units | Chew Weng Leong, Chee Kiang Yew, Pang Hup Ong, Jeffrey Toh, Boon Pew Chan | 2002-10-22 |
| 6387729 | Method for adhering and sealing a silicon chip in an integrated circuit package | Kian Teng Eng, Jing Sua Goh, Siu Waf Low, Boon Pew Chan, Tuck Fook Toh +2 more | 2002-05-14 |
| 6365833 | Integrated circuit package | Kian Teng Eng, Jing Sua Goh, Siu Waf Low, Boon Pew Chan, Tuck Fook Toh +2 more | 2002-04-02 |
| 6274929 | Stacked double sided integrated circuit package | Chew Weng Leong, Chee Kiang Yew, Pang Hup Ong, Jeffrey Toh, Boon Pew Chan | 2001-08-14 |
| 6236107 | Encapsulate resin LOC package and method of fabrication | Siu Waf Low, Jing Sua Goh | 2001-05-22 |
| 6218202 | Semiconductor device testing and burn-in methodology | Chee Kiang Yew, Kim Hoch Tey, Jeffrey Toh | 2001-04-17 |
| 6177723 | Integrated circuit package and flat plate molding process for integrated circuit package | Kian Teng Eng, Jing Sua Goh, Boon Pew Chan | 2001-01-23 |
| 6137164 | Thin stacked integrated circuit device | Chee Yew, Siu Waf Low | 2000-10-24 |
| 6087203 | Method for adhering and sealing a silicon chip in an integrated circuit package | Kian Teng Eng, Jing Sua Goh, Siu Waf Low, Boon Pew Chan, Tuck Fook Toh +2 more | 2000-07-11 |
| 6049129 | Chip size integrated circuit package | Chee Kiang Yew, Yong Khim Swee, Pang Hup Ong, Anthony L. Coyle | 2000-04-11 |
| 6040623 | Slotted lead for a semiconductor device | Jing Sua Goh | 2000-03-21 |
| 5952611 | Flexible pin location integrated circuit package | Kian Teng Eng, Jing Sua Goh, Siu Waf Low | 1999-09-14 |
| 5647124 | Method of attachment of a semiconductor slotted lead to a substrate | Jing Sua Goh | 1997-07-15 |
| 5461255 | Multi-layered lead frame assembly for integrated circuits | Siu Waf Low | 1995-10-24 |
| 5293065 | Lead frame having an outlet with a larger cross sectional area than the inlet | — | 1994-03-08 |