Issued Patents All Time
Showing 51–75 of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8900956 | Method of dual EPI process for semiconductor device | Han-Pin Chung, Bor Chiuan Hsieh, Ming-Jie Huang | 2014-12-02 |
| 8900957 | Method of dual epi process for semiconductor device | Han-Pin Chung, Bor Chiuan Hsieh, Ming-Jie Huang | 2014-12-02 |
| 8853817 | Isolation structure profile for gap filing | — | 2014-10-07 |
| 8822304 | Isolation structure profile for gap filing | — | 2014-09-02 |
| 8759919 | End-to-end gap fill using dielectric film | — | 2014-06-24 |
| 8609497 | Method of dual EPI process for semiconductor device | Han-Pin Chung, Bor Chiuan Hsieh, Ming-Jie Huang | 2013-12-17 |
| 8604562 | Post CMP planarization by cluster ion beam etch | — | 2013-12-10 |
| 8598661 | Epitaxial process for forming semiconductor devices | — | 2013-12-03 |
| 8598675 | Isolation structure profile for gap filling | — | 2013-12-03 |
| 8569185 | Method of fabricating gate electrode using a treated hard mask | Matt Yeh, Hui Ouyang, Han-Pin Chung | 2013-10-29 |
| 8518786 | Process for forming a metal oxide semiconductor devices | — | 2013-08-27 |
| 8461015 | STI structure and method of forming bottom void in same | Yu-Lien Huang, Han-Pin Chung | 2013-06-11 |
| 8404534 | End-to-end gap fill using dielectric film | — | 2013-03-26 |
| 8389371 | Method of fabricating integrated circuit device, including removing at least a portion of a spacer | — | 2013-03-05 |
| 8383485 | Epitaxial process for forming semiconductor devices | — | 2013-02-26 |
| 8372755 | Multilayer hard mask | Hun-Jan Tao | 2013-02-12 |
| 8361338 | Hard mask removal method | — | 2013-01-29 |
| 8193094 | Post CMP planarization by cluster ION beam etch | — | 2012-06-05 |
| 8093146 | Method of fabricating gate electrode using a hard mask with spacers | — | 2012-01-10 |
| 8071481 | Method for forming highly strained source/drain trenches | Ta-Wei Kao, Ming-Jie Huang, Chi-Hsi Wu, Shu-Yuan Ku | 2011-12-06 |
| 7947551 | Method of forming a shallow trench isolation structure | Sen-Hong Syue, Bor Chiuan Hsieh | 2011-05-24 |
| 7732878 | MOS devices with continuous contact etch stop layer | Liang-Gi Yao, Huan-Just Lin, Peng-Fu Hsu, Jin Ying, Hun-Jan Tao | 2010-06-08 |
| 7301645 | In-situ critical dimension measurement | Yuan-Hung Chiu, Hun-Jan Tao, Chao-Tzung Tsai | 2007-11-27 |
| 7109085 | Etching process to avoid polysilicon notching | Li-Te Lin, Ming-Ching Chang, Ryan Chia-Jen Chen, Yuan-Hung Chiu, Hun-Jan Tao | 2006-09-19 |
| 6677712 | Gas distribution plate electrode for a plasma receptor | Dan Katz, Douglas A. Buchberger, Jr., Yan Ye, Robert B. Hagen, Xiaoye Zhao +3 more | 2004-01-13 |