Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12369390 | Method for forming semiconductor structure with high aspect ratio | Chih-Tang Peng, Tien-I Bao | 2025-07-22 |
| 11823960 | Method for forming semiconductor structure with high aspect ratio | Chih-Tang Peng, Tien-I Bao | 2023-11-21 |
| 10872961 | Semiconductor device and manufacturing method thereof | — | 2020-12-22 |
| 10840154 | Method for forming semiconductor structure with high aspect ratio | Chih-Tang Peng, Tien-I Bao | 2020-11-17 |
| 10629497 | FinFET device structure and method for enlarging gap-fill window | Jian-Shiou Huang | 2020-04-21 |
| 9659776 | Doping for FinFET | Hung-Kai Chen, Tsung-Hung Lee, Shih-Syuan Huang, Chun-Fu Cheng, Chien-Tai Chan +3 more | 2017-05-23 |
| 9362404 | Doping for FinFET | Hung-Kai Chen, Tsung-Hung Lee, Shih-Syuan Huang, Chun-Fu Cheng, Chien-Tai Chan +3 more | 2016-06-07 |
| 9218974 | Sidewall free CESL for enlarging ILD gap-fill window | Bor Chiuan Hsieh, Shiang-Bau Wang, Hun-Jan Tao | 2015-12-22 |
| 8999834 | Sidewall-free CESL for enlarging ILD gap-fill window | Bor Chiuan Hsieh, Shiang-Bau Wang, Hun-Jan Tao | 2015-04-07 |
| 8900956 | Method of dual EPI process for semiconductor device | Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang | 2014-12-02 |
| 8900957 | Method of dual epi process for semiconductor device | Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang | 2014-12-02 |
| 8609497 | Method of dual EPI process for semiconductor device | Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang | 2013-12-17 |
| 8569185 | Method of fabricating gate electrode using a treated hard mask | Matt Yeh, Hui Ouyang, Shiang-Bau Wang | 2013-10-29 |
| 8461015 | STI structure and method of forming bottom void in same | Yu-Lien Huang, Shiang-Bau Wang | 2013-06-11 |