Issued Patents All Time
Showing 201–225 of 227 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9355977 | Bump structures for semiconductor package | Jing-Cheng Lin | 2016-05-31 |
| 9349701 | Self-aligning conductive bump structure and method of fabrication | Cheng-Lin Huang, I-Ting Chen, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin +2 more | 2016-05-24 |
| 9318455 | Method of forming a plurality of bumps on a substrate and method of forming a chip package | Jing-Cheng Lin | 2016-04-19 |
| 9252065 | Mechanisms for forming package structure | Jing-Cheng Lin | 2016-02-02 |
| 9219016 | Structure design for 3DIC testing | Jing-Cheng Lin | 2015-12-22 |
| 9159678 | Semiconductor device and manufacturing method thereof | Li-Hui Cheng, Jui-Pin Hung | 2015-10-13 |
| 9142432 | Integrated fan-out package structures with recesses in molding compound | Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin | 2015-09-22 |
| 9111821 | Packaged semiconductor devices and packaging devices and methods | Jing-Cheng Lin | 2015-08-18 |
| 9111914 | Fan out package, semiconductor device and manufacturing method thereof | Jing-Cheng Lin, Jui-Pin Hung | 2015-08-18 |
| 9093314 | Copper bump structures having sidewall protection layers | Jing-Cheng Lin, Ya-Hsi Hwung, Hsin-Yu Chen, Yan-Fu Lin, Cheng-Lin Huang +2 more | 2015-07-28 |
| 9048222 | Method of fabricating interconnect structure for package-on-package devices | Jui-Pin Hung, Jing-Cheng Lin, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh +1 more | 2015-06-02 |
| 9024438 | Self-aligning conductive bump structure and method of making the same | Cheng-Lin Huang, I-Ting Chen, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin +2 more | 2015-05-05 |
| 8970035 | Bump structures for semiconductor package | Jing-Cheng Lin | 2015-03-03 |
| 8953336 | Surface metal wiring structure for an IC substrate | Chin-Fu Kao, Wen-Chih Chiou, Jing-Cheng Lin, Cheng-Lin Huang | 2015-02-10 |
| 8952544 | Semiconductor device and manufacturing method thereof | Jing-Cheng Lin, Jui-Pin Hung | 2015-02-10 |
| 8941244 | Semiconductor device and manufacturing method thereof | Jui-Pin Hung, Jing-Cheng Lin, Long Hua Lee | 2015-01-27 |
| 8922004 | Copper bump structures having sidewall protection layers | Jing-Cheng Lin, Ya-Hsi Hwung, Hsin-Yu Chen, Yan-Fu Lin, Cheng-Lin Huang +2 more | 2014-12-30 |
| 8901735 | Connector design for packaging integrated circuits | Chen-Hua Yu, Ying-Ching Shih, Chin-Fu Kao, Cheng-Lin Huang, Cheng-Chieh Hsieh +4 more | 2014-12-02 |
| 8877554 | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices | Jui-Pin Hung, Jing-Cheng Lin | 2014-11-04 |
| 8778738 | Packaged semiconductor devices and packaging devices and methods | Jing-Cheng Lin | 2014-07-15 |
| 8664760 | Connector design for packaging integrated circuits | Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Cheng-Chieh Hsieh, Kuo-Ching Hsu +4 more | 2014-03-04 |
| 8653658 | Planarized bumps for underfill control | Jing-Cheng Lin | 2014-02-18 |
| 8610285 | 3D IC packaging structures and methods with a metal pillar | Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Kuo-Ching Hsu, Cheng-Chieh Hsieh +3 more | 2013-12-17 |
| 8455995 | TSVs with different sizes in interposers for bonding dies | Jing-Cheng Lin, Chen-Hua Yu | 2013-06-04 |
| 7125795 | Fabrication method for microstructures with high aspect ratios | Nai-Hao Kuo, Kai-Hsiang Yen, Jing-Hung Chiou, Yuh-Wen Lee | 2006-10-24 |