Issued Patents All Time
Showing 76–100 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10510591 | Package-on-package structure and method of manufacturing package | Chin-Fu Kao, Chih-Yuan Chien, Szu-Wei Lu | 2019-12-17 |
| 10504824 | Integrated circuit package and method | Chih-Chien Pan, Chin-Fu Kao, Szu-Wei Lu | 2019-12-10 |
| 10438934 | Package-on-package structure and manufacturing method thereof | Shih-Ting Lin, Chin-Fu Kao, Jing-Cheng Lin, Szu-Wei Lu | 2019-10-08 |
| 10354982 | Integrated fan-out structure with guiding trenches in buffer layer | Po-Hao Tsai, Feng-Cheng Hsu, Jui-Pin Hung, Jing-Cheng Lin | 2019-07-16 |
| 10290610 | PoP device and method of forming the same | Li-Hsien Huang, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Po-Hao Tsai +2 more | 2019-05-14 |
| 10269587 | Integrated circuit packages and methods of forming same | Jing-Cheng Lin, Po-Hao Tsai | 2019-04-23 |
| 10170341 | Release film as isolation film in package | Jing-Cheng Lin, Po-Hao Tsai | 2019-01-01 |
| 10163848 | Semiconductor package | Jing-Cheng Lin, Po-Hao Tsai, Chih-Chien Pan | 2018-12-25 |
| 10163875 | Method for forming chip package structure with adhesive layer | Po-Hao Tsai, Jing-Cheng Lin, Yi-Hang Lin | 2018-12-25 |
| 10134719 | Semiconductor package and manufacturing method thereof | Jing-Cheng Lin, Po-Hao Tsai | 2018-11-20 |
| 10115675 | Packaged semiconductor device and method of fabricating a packaged semiconductor device | Jing-Cheng Lin, Po-Hao Tsai | 2018-10-30 |
| 10103132 | Semiconductor device and method of manufactures | Jing-Cheng Lin, Po-Hao Tsai | 2018-10-16 |
| 10083946 | Integrated fan-out structure with guiding trenches in buffer layer | Po-Hao Tsai, Feng-Cheng Hsu, Jui-Pin Hung, Jing-Cheng Lin | 2018-09-25 |
| 10079159 | Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package | Jing-Cheng Lin, Jui-Pin Hung | 2018-09-18 |
| 10079225 | Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package | Jing-Cheng Lin, Jui-Pin Hung | 2018-09-18 |
| 10062662 | Integrated fan-out package structures with recesses in molding compound | Po-Hao Tsai, Jui-Pin Hung, Jing-Cheng Lin | 2018-08-28 |
| 10008485 | Semiconductor device and method of manufacture | Jing-Cheng Lin, Po-Hao Tsai, Porter Chen | 2018-06-26 |
| 9953955 | Integrated fan-out package structures with recesses in molding compound | Po-Hao Tsai, Jui-Pin Hung, Jing-Cheng Lin | 2018-04-24 |
| 9929128 | Chip package structure with adhesive layer | Po-Hao Tsai, Jing-Cheng Lin, Yi-Hang Lin | 2018-03-27 |
| 9799581 | Integrated fan-out structure with openings in buffer layer | Wu Sen Chiu, Po-Hao Tsai, Jing-Cheng Lin | 2017-10-24 |
| 9761566 | Multi-die structure and method of forming same | Chen-Hua Yu, Po-Hao Tsai, Jing-Cheng Lin | 2017-09-12 |
| 9646918 | Semiconductor device and method | Po-Hao Tsai, Jing-Cheng Lin | 2017-05-09 |
| 9633934 | Semicondutor device and method of manufacture | Jing-Cheng Lin, Po-Hao Tsai, Porter Chen | 2017-04-25 |
| 9633895 | Integrated fan-out structure with guiding trenches in buffer layer | Po-Hao Tsai, Feng-Cheng Hsu, Jui-Pin Hung, Jing-Cheng Lin | 2017-04-25 |
| 9583420 | Semiconductor device and method of manufactures | Jing-Cheng Lin, Po-Hao Tsai | 2017-02-28 |