Issued Patents All Time
Showing 26–50 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10199512 | High voltage withstand Ga2O3-based single crystal schottky barrier diode | Kohei Sasaki, Masataka Higashiwaki, Akinori Koukitu, Yoshinao Kumagai, Hisashi Murakami | 2019-02-05 |
| 10193090 | Method of manufacturing a semiconductor device and a semiconductor device | Chun-Chieh Lu, Jean-Pierre Colinge, Zhiqiang Wu, Yu-Ming Lin | 2019-01-29 |
| 10157985 | MOSFET with selective dopant deactivation underneath gate | Dhanyakumar Mahaveer Sathaiya, Kai-Chieh Yang, Wei-Hao Wu, Zhiqiang Wu, Yuan-Chen Sun | 2018-12-18 |
| 10134915 | 2-D material transistor with vertical structure | Jean-Pierre Colinge, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Ta-Pen Guo +3 more | 2018-11-20 |
| 10084066 | Semiconductor device and manufacturing method thereof | Yu-Ming Lin | 2018-09-25 |
| 10000373 | Nano-electromechanical system (NEMS) device structure and method for forming the same | Hsin-Ping Chen, Carlos H. Diaz, Shau-Lin Shue, Tai-I Yang | 2018-06-19 |
| 9899517 | Dislocation stress memorization technique (DSMT) on epitaxial channel devices | Tsung-Hsing Yu, Shih-Syuan Huang, Yi-Ming Sheu | 2018-02-20 |
| 9899475 | Epitaxial channel with a counter-halo implant to improve analog gain | Tsung-Hsing Yu, Shih-Syuan Huang, Yi-Ming Sheu | 2018-02-20 |
| 9853150 | Method of fabricating epitaxial gate dielectrics and semiconductor device of the same | Jean-Pierre Colinge, Zhiqiang Wu | 2017-12-26 |
| 9768297 | Process design to improve transistor variations and performance | Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu, Shih-Syuan Huang, Zhiqiang Wu | 2017-09-19 |
| 9716172 | Semiconductor device having multiple active area layers and its formation thereof | Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu | 2017-07-25 |
| 9704532 | Creating and viewing preview objects | Andy Hakim | 2017-07-11 |
| 9660049 | Semiconductor transistor device with dopant profile | Tsung-Hsing Yu, Chia-Wen Liu | 2017-05-23 |
| 9653545 | MOSFET structure with T-shaped epitaxial silicon channel | Mahaveer Sathaiya Dhanyakumar, Wei-Hao Wu, Tsung-Hsing Yu, Chia-Wen Liu, Tzer-Min Shen +1 more | 2017-05-16 |
| 9553150 | Transistor design | Wen-Yuan Chen, Tsung-Hsing Yu, Zhiqiang Wu | 2017-01-24 |
| 9536746 | Recess and epitaxial layer to improve transistor performance | Yeh Hsu, Chia-Wen Liu, Tsung-Hsing Yu, Shih-Syuan Huang | 2017-01-03 |
| 9525031 | Epitaxial channel | Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu | 2016-12-20 |
| 9502409 | Multi-gate semiconductor devices | Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu +3 more | 2016-11-22 |
| 9502559 | Dislocation stress memorization technique (DSMT) on epitaxial channel devices | Tsung-Hsing Yu, Shih-Syuan Huang, Yi-Ming Sheu | 2016-11-22 |
| 9425099 | Epitaxial channel with a counter-halo implant to improve analog gain | Tsung-Hsing Yu, Shih-Syuan Huang, Yi-Ming Sheu | 2016-08-23 |
| 9419136 | Dislocation stress memorization technique (DSMT) on epitaxial channel devices | Tsung-Hsing Yu, Shih-Syuan Huang, Yi-Ming Sheu | 2016-08-16 |
| 9318322 | FinFET design controlling channel thickness | Zhiqiang Wu, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang | 2016-04-19 |
| 9263345 | SOI transistors with improved source/drain structures with enhanced strain | Dhanyakumar Mahaveer Sathaiya, Ching-Chang Wu, Tzer-Min Shen | 2016-02-16 |
| 9236445 | Transistor having replacement gate and epitaxially grown replacement channel region | Chia-Wen Liu, Tsung-Hsing Yu, Wei-Hao Wu, Meikei Ieong, Zhiqiang Wu | 2016-01-12 |
| 9224814 | Process design to improve transistor variations and performance | Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu, Shih-Syuan Huang, Zhiqiang Wu | 2015-12-29 |