Issued Patents All Time
Showing 176–195 of 195 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8518819 | Semiconductor device contact structures and methods for making the same | Shih-Chieh Chang, Chih-Chung Chang, Ying-Lang Wang | 2013-08-27 |
| 8470390 | Oxidation-free copper metallization process using in-situ baking | Yu-Sheng Wang, Shih-Ho Lin, Szu-An Wu, Ying-Lang Wang | 2013-06-25 |
| 8455883 | Stressed semiconductor device and method of manufacturing | Miao-Cheng Liao, Min Hao Hong, Hsiang Hsiang Ko, Ying-Lang Wang | 2013-06-04 |
| 8247322 | Via/contact and damascene structures and manufacturing methods thereof | Shih-Chieh Chang, Ying-Lang Wang, Jung-Chih Tsao, Yu-Sheng Wang | 2012-08-21 |
| 8099861 | Current-leveling electroplating/electropolishing electrode | Shih-Chieh Chang, Ying-Lang Wang, Shih-Ho Lin, Chun-Chang Chen | 2012-01-24 |
| 7969708 | Alpha tantalum capacitor plate | Jung-Chih Tsao, Miao-Cheng Liao, Phil Sun | 2011-06-28 |
| 7837841 | Apparatuses for electrochemical deposition, conductive layer, and fabrication methods thereof | Mu-Han Cheng, Jian-Sin Tsai, Ying-Lang Wang | 2010-11-23 |
| 7803257 | Current-leveling electroplating/electropolishing electrode | Shih-Chieh Chang, Ying-Lang Wang, Shih-Ho Lin, Chun-Chang Chen | 2010-09-28 |
| 7417321 | Via structure and process for forming the same | Jung-Chih Tsao, Ying-Jing Lu, Yu-Sheng Wang, Yu-Ku Lin | 2008-08-26 |
| 7368379 | Multi-layer interconnect structure for semiconductor devices | Jung-Chih Tsao, Yu-Ku Lin, Chyi Shyuan Chern | 2008-05-06 |
| 7312149 | Copper plating of semiconductor devices using single intermediate low power immersion step | Chao-Lung Chen, Shih-Ho Lin, Ying-Lang Wang, Yu-Ku Lin, Ching-Hwanq Su +2 more | 2007-12-25 |
| 7304728 | Test device and method for laser alignment calibration | Shih-Tzung Chang, Yu-Ku Lin, Shih-Ho Lin, Ting-Chun Wang, Ching-Hwan Su +1 more | 2007-12-04 |
| 7208404 | Method to reduce Rs pattern dependence effect | Jung-Chih Tsao, Chi-Wen Li, Jye-Wei Hsu, Hsien-Pin Fong, Steven Lin +1 more | 2007-04-24 |
| 7199045 | Metal-filled openings for submicron devices and methods of manufacture thereof | Chi-Wen Liu, Jung-Chih Tsao, Shih-Tzung Chang, Ying-Lang Wang | 2007-04-03 |
| 7183199 | Method of reducing the pattern effect in the CMP process | Chi-Wen Liu, Jung-Chih Tsao, Shien-Ping Feng, Shih-Chi Lin, Ray Chuang | 2007-02-27 |
| 7128821 | Electropolishing method for removing particles from wafer surface | Shih-Ho Lin, Chung-Chang Chen, Shih-Tzung Chang, Chao-Lung Chen, Po-Jen Shih +2 more | 2006-10-31 |
| 7071100 | Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process | Jung-Chih Tsao, Chi-Wen Liu, Jchung-Chang Chen, Shih-Tzung Chang, Shih-Ho Lin +2 more | 2006-07-04 |
| 6828226 | Removal of SiON residue after CMP | Kuo-Hsiu Wei, Yu-Kin Lin, Ting-Chun Wang, Ying-Lang Wang, Shih-Tzung Chang | 2004-12-07 |
| 6769959 | Method and system for slurry usage reduction in chemical mechanical polishing | Ting-Chun Wang, Shih-Tzung Chang, Yu-Ku Lin, Ying-Lang Wang, Ming-Wen Chen +1 more | 2004-08-03 |
| 6626741 | Method for improving thickness uniformity on a semiconductor wafer during chemical mechanical polishing | Ting-Chun Wang, Shih-Tzung Chang, Yu-Ku Lin, Ying-Lang Wang | 2003-09-30 |