Issued Patents All Time
Showing 276–298 of 298 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8227869 | Performance-aware logic operations for generating masks | Lee-Chung Lu, Yen-Sen Wang, Yao-Jen Chuang, Gwan Sin Chang | 2012-07-24 |
| 8216905 | Stress engineering to reduce dark current of CMOS image sensors | Ru-Shang Hsiao, Nai-Wen Cheng, Chien-Hsien Tseng, Shou-Gwo Wuu | 2012-07-10 |
| 8158474 | Semiconductor device with localized stressor | Ru-Shang Hsiao, Min Cao, Ta-Ming Kuan, Cheng-Tung Hsu | 2012-04-17 |
| 8122394 | Performance-aware logic operations for generating masks | Lee-Chung Lu, Yen-Sen Wang, Yao-Jen Chuang, Gwan Sin Chang | 2012-02-21 |
| 7943961 | Strain bars in stressed layers of MOS devices | Yen-Sen Wang, Min Cao, Sheng-Jier Yang | 2011-05-17 |
| 7825477 | Semiconductor device with localized stressor | Ru-Shang Hsiao, Min Cao, Ta-Ming Kuan, Cheng-Tung Hsu | 2010-11-02 |
| 7732298 | Metal salicide formation having nitride liner to reduce silicide stringer and encroachment | Tan-Chen Lee, Kuang-Hsin Chen, Chi-Hsi Wu, Di-Houng Lee, Cheng-Hung Chang | 2010-06-08 |
| 7611937 | High performance transistors with hybrid crystal orientations | I-Lu Wu, Mariam Sadaka | 2009-11-03 |
| 7449386 | Manufacturing method for semiconductor device to mitigate short channel effects | Di-Houng Lee, Yee-Chaung See | 2008-11-11 |
| 7432149 | CMOS on SOI substrates with hybrid crystal orientations | I-Lu Wu, Tan-Chen Lee | 2008-10-07 |
| 6797587 | Active region corner implantation method for fabricating a semiconductor integrated circuit microelectronic fabrication | Feng-Cheng Yang, Yea-Dean Sheu, Chih-Hung Wang | 2004-09-28 |
| 6790756 | Self aligned channel implant, elevated S/D process by gate electrode damascene | Chu-Wei Hu, Jiue-Wen Weng, So Wein Kuo | 2004-09-14 |
| 6583017 | Self aligned channel implant, elevated S/D process by gate electrode damascene | Chu-Wei Hu, Jiue-Wen Weng, So Wein Kuo | 2003-06-24 |
| 6444544 | Method of forming an aluminum protection guard structure for a copper metal structure | Chu-Wei Hu, Kuo-Hua Pan, Hsien-Chin Lin | 2002-09-03 |
| 6444541 | Method for forming lining oxide in shallow trench isolation incorporating pre-annealing step | Jun-Yang Lai, Jih-Hwa Wang, Chou-Jie Tsai, Chin-Te Huang, Su-Yu Yeh +2 more | 2002-09-03 |
| 6287926 | Self aligned channel implant, elevated S/D process by gate electrode damascene | Chu-Wei Hu, Jiue-Wen Weng, So Wein Kuo | 2001-09-11 |
| 6207538 | Method for forming n and p wells in a semiconductor substrate using a single masking step | Kuo-Hua Pan, Chu-Wei Hu, Chin-Hsiung Ho | 2001-03-27 |
| 6194285 | Formation of shallow trench isolation (STI) | Kong-Bong Thei, Carlos H. Diaz | 2001-02-27 |
| 6103581 | Method for producing shallow trench isolation structure | Chin-Hsiung Ho, Hann-Huei Tsai | 2000-08-15 |
| 6080638 | Formation of thin spacer at corner of shallow trench isolation (STI) | Shwangming Jeng, Yuan-Horng Chiu, Kong-Beng Thei | 2000-06-27 |
| 6074905 | Formation of a thin oxide protection layer at poly sidewall and area surface | Chu-Wei Hu, Chin-Shan Hou, Kuo-Hua Pan | 2000-06-13 |
| 6063695 | Simplified process for the fabrication of deep clear laser marks using a photoresist mask | Chin-Hsiung Ho, Hsueh-Liang Chiu, So Wein Kuo | 2000-05-16 |
| 6057207 | Shallow trench isolation process using chemical-mechanical polish with self-aligned nitride mask on HDP-oxide | Chin H. Ho | 2000-05-02 |