Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9412871 | FinFET with channel backside passivation layer device and method | Gerben Doornbos, Mark van Dal, Georgios Vellianitis, Blandine Duriez, Krishna Kumar Bhuwalka +3 more | 2016-08-09 |
| 7449386 | Manufacturing method for semiconductor device to mitigate short channel effects | Chung-Te Lin, Di-Houng Lee | 2008-11-11 |
| 5929478 | Single level gate nonvolatile memory device and method for accessing the same | Patrice M. Parris, Irenee Pages, Juan Buxo, Eric Carman, Thierry Sicard +1 more | 1999-07-27 |
| 5892709 | Single level gate nonvolatile memory device and method for accessing the same | Patrice M. Parris | 1999-04-06 |
| 5777361 | Single gate nonvolatile memory cell and method for accessing the same | Patrice M. Parris | 1998-07-07 |
| 5674762 | Method of fabricating an EPROM with high voltage transistors | Lewis E. Terry, Craig A. Cavins | 1997-10-07 |
| 5604700 | Non-volatile memory cell having a single polysilicon gate | Patrice M. Parris | 1997-02-18 |
| 5358883 | Lateral bipolar transistor | Wayne R. Burger | 1994-10-25 |
| 5279978 | Process for making BiCMOS device having an SOI substrate | Thomas C. Mele, John R. Alvis | 1994-01-18 |
| 5212397 | BiCMOS device having an SOI substrate and process for making the same | Thomas C. Mele, John R. Alvis | 1993-05-18 |
| 5112772 | Method of fabricating a trench structure | Syd R. Wilson, Han-Bin K. Liang, Thomas E. Zirkle | 1992-05-12 |
| 4775642 | Modified source/drain implants in a double-poly non-volatile memory process | Kuang-Yeh Chang, Charles Frederick Hart | 1988-10-04 |
| 4476482 | Silicide contacts for CMOS devices | David B. Scott, Roderick D. Davies | 1984-10-09 |
| 4418094 | Vertical-etch direct moat isolation process | Roderick D. Davies, Dennis C. Hartman | 1983-11-29 |
| 4374700 | Method of manufacturing silicide contacts for CMOS devices | David B. Scott, Roderick D. Davies | 1983-02-22 |