Issued Patents All Time
Showing 26–50 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11972814 | Verify techniques for current reduction in a memory device | Xue Bai Pitner, Ravi Kumar, Jiahui Yuan, Bo Lei, Zhenni Wan | 2024-04-30 |
| 11972809 | Selective inhibit bitline voltage to cells with worse program disturb | Sujjatul Islam, Ravi Kumar, Xue Bai Pitner | 2024-04-30 |
| 11972803 | Word line zone dependent pre-charge voltage | Fanqi Wu, Jiahui Yuan | 2024-04-30 |
| 11972801 | Program voltage dependent program source levels | Xue Bai Pitner, Sarath Puthenthermadam, Sujjatul Islam | 2024-04-30 |
| 11972122 | Memory read operation using a voltage pattern based on a read command type | Ching-Huang Lu, Zhenming Zhou | 2024-04-30 |
| 11894081 | EP cycling dependent asymmetric/symmetric VPASS conversion in non-volatile memory structures | Xue Bai Pitner, Ken Oowada | 2024-02-06 |
| 11887670 | Controlling bit line pre-charge voltage separately for multi-level memory cells and single-level memory cells to reduce peak current consumption | Deepanshu Dutta, Jiahui Yuan | 2024-01-30 |
| 11875842 | Systems and methods for staggering read operation of sub-blocks | Deepanshu Dutta, Tai-Yuan Tseng | 2024-01-16 |
| 11837296 | Non-volatile memory with adjusted bit line voltage during verify | Jiahui Yuan, Ohwon Kwon | 2023-12-05 |
| 11790992 | State dependent VPVD voltages for more uniform threshold voltage distributions in a memory device | Huai-Yuan Tseng | 2023-10-17 |
| 11758718 | Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines | Abhijith Prakash, Keyur Payak, Jiahui Yuan, Huai-Yuan Tseng, Shinsuke Yada +1 more | 2023-09-12 |
| 11699494 | Peak and average ICC reduction by tier-based sensing during program verify operations of non-volatile memory structures | Xue Bai Pitner, Deepanshu Dutta, Huai-Yuan Tseng, Ravi Kumar | 2023-07-11 |
| 11664075 | Sub-block programming mode with multi-tier block | Jiahui Yuan, Tomer Eliash | 2023-05-30 |
| 11600343 | Efficient read of NAND with read disturb mitigation | Tomer Eliash, Huai-Yuan Tseng | 2023-03-07 |
| 11587619 | Block configuration for memory device with separate sub-blocks | Jiahui Yuan, Deepanshu Dutta | 2023-02-21 |
| 11521686 | Memory apparatus and method of operation using state bit-scan dependent ramp rate for peak current reduction during program operation | Hua-Ling Cynthia Hsu, Huai-Yuan Tseng, Fanglin Zhang | 2022-12-06 |
| 11508450 | Dual time domain control for dynamic staggering | Huai-Yuan Tseng, Deepanshu Dutta | 2022-11-22 |
| 11475959 | Reduced program time for memory cells using negative bit line voltage for enhanced step up of program bias | Sujjatul Islam, Xue Bai Pitner | 2022-10-18 |
| 11475958 | Negative bit line biasing during quick pass write programming | Huai-Yuan Tseng, Swaroop Kaza, Tomer Eliash | 2022-10-18 |
| 11456333 | Three-dimensional NAND memory device containing two terminal selector and methods of using and making thereof | Jiahui Yuan, Deepanshu Dutta, Christopher J. Petti | 2022-09-27 |
| 11417400 | Controlling timing and ramp rate of program-inhibit voltage signal during programming to optimize peak current | Huai-Yuan Tseng, Deepanshu Dutta | 2022-08-16 |
| 11398280 | Lockout mode for reverse order read operation | Deepanshu Dutta, Huai-Yuan Tseng, Ravi Kumar | 2022-07-26 |
| 11386968 | Memory apparatus and method of operation using plane dependent ramp rate and timing control for program operation | Huai-Yuan Tseng, Tomer Eliash | 2022-07-12 |
| 11385810 | Dynamic staggering for programming in nonvolatile memory | Deepanshu Dutta, Huai-Yuan Tseng | 2022-07-12 |
| 11373710 | Time division peak power management for non-volatile storage | Hua-Ling Cynthia Hsu, Mark Murin, Mark Shlick | 2022-06-28 |