Issued Patents All Time
Showing 51–74 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11361835 | Countermeasure for reducing peak current during programming by optimizing timing of latch scan operations | Fanglin Zhang, Huai-Yuan Tseng | 2022-06-14 |
| 11355208 | Triggering next state verify in progam loop for nonvolatile memory | Fanglin Zhang, Zhuojie Li, Huai-Yuan Tseng | 2022-06-07 |
| 11335411 | Erase operation for memory device with staircase word line voltage during erase pulse | Keyur Payak, Huai-Yuan Tseng | 2022-05-17 |
| 11335413 | Ramp rate control for peak and average current reduction of open blocks | Huai-Yuan Tseng, Deepanshu Dutta | 2022-05-17 |
| 11328754 | Pre-charge timing control for peak current based on data latch count | Juan Lee, Huai-Yuan Tseng | 2022-05-10 |
| 11315648 | Dynamic tier selection for program verify in nonvolatile memory | Dengtao Zhao, Huai-Yuan Tseng | 2022-04-26 |
| 11270776 | Countermeasure for reducing peak current during program operation under first read condition | Huai-Yuan Tseng, Deepanshu Dutta | 2022-03-08 |
| 11250892 | Pre-charge ramp rate control for peak current based on data latch count | Juan Lee, Huai-Yuan Tseng | 2022-02-15 |
| 11226772 | Peak power reduction management in non-volatile storage by delaying start times operations | Mark Murin, Hua-Ling Cynthia Hsu, Tomer Eliash, Huai-Yuan Tseng, Deepanshu Dutta | 2022-01-18 |
| 11211127 | Loop dependent plane skew methodology for program operation | Hua-Ling Cynthia Hsu, Huai-Yuan Tseng | 2021-12-28 |
| 11189351 | Peak and average current reduction for sub block memory operation | Sarath Puthenthermadam, Huai-Yuan Tseng | 2021-11-30 |
| 11189337 | Multi-stage voltage control for peak and average current reduction of open blocks | Huai-Yuan Tseng, Deepanshu Dutta | 2021-11-30 |
| 11114178 | Physical defect detection in an integrated memory assembly | Tomer Eliash, Alexander Bazarsky, Eran Sharon | 2021-09-07 |
| 11107901 | Charge storage memory device including ferroelectric layer between control gate electrode layers and methods of making the same | Jiahui Yuan, Deepanshu Dutta | 2021-08-31 |
| 11081162 | Source side precharge and boosting improvement for reverse order program | Sarath Puthenthermadam, Huai-Yuan Tseng | 2021-08-03 |
| 11081197 | Wordline voltage overdrive methods and systems | Xiang Yang | 2021-08-03 |
| 11037635 | Power management for multi-plane read operations | Tomer Eliash, Huai-Yuan Tseng | 2021-06-15 |
| 10902925 | Peak and average current reduction for open block condition | Michael Tseng, Deepanshu Dutta | 2021-01-26 |
| 10878923 | Partial page sensing mode, method, and apparatus for 3D NAND | Xiang Yang | 2020-12-29 |
| 10861571 | Wordline voltage overdrive methods and systems | Xiang Yang | 2020-12-08 |
| 10861537 | Countermeasures for first read issue | Huai-Yuan Tseng, Deepanshu Dutta, Abhijith Prakash | 2020-12-08 |
| 10727276 | Three-dimensional NAND memory device containing two terminal selector and methods of using and making thereof | Jiahui Yuan, Deepanshu Dutta, Christopher J. Petti | 2020-07-28 |
| 10636498 | Managing bit-line settling time in non-volatile memory | Xiang Yang, Zhenming Zhou, Deepanshu Dutta | 2020-04-28 |
| 10541038 | Subgroup selection for verification | Xiang Yang, Zhenming Zhou, Deepanshu Dutta, Huai-Yuan Tseng | 2020-01-21 |