Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9972641 | Three-dimensional memory device having a multilevel drain select gate electrode and method of making thereof | Yanli Zhang, Jin Liu, Raghuveer S. Makala, Johann Alsmeier | 2018-05-15 |
| 9972640 | Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof | James Kai, Jin Liu, Johann Alsmeier | 2018-05-15 |
| 9748235 | Gate stack for integrated circuit structure and method of forming same | Aritra Dasgupta, Benjamin G. Moser, Mohammad Hasanuzzaman, Shahrukh Khan, Shafaat Ahmed +1 more | 2017-08-29 |
| 9698153 | Vertical NAND and method of making thereof using sequential stack etching and self-aligned landing pad | Jin Liu, Yanli Zhang, Raghuveer S. Makala, Johann Alsmeier | 2017-07-04 |
| 9576975 | Monolithic three-dimensional NAND strings and methods of fabrication thereof | Yanli Zhang, James Kai, Raghuveer S. Makala, Jin Liu, Camilla Huang +1 more | 2017-02-21 |
| 9570463 | Multilevel memory stack structure with joint electrode having a collar portion and methods for manufacturing the same | Yanli Zhang, Raghuveer S. Makala, Jin Liu, Yao-Sheng Lee, Johann Alsmeier | 2017-02-14 |
| 9431485 | Formation of finFET junction | Shafaat Ahmed, Aritra Dasgupta, Mohammad Hasanuzzaman, Shahrukh Khan, Joyeeta Nag | 2016-08-30 |
| 9397111 | Select gate transistor with single crystal silicon for three-dimensional memory | Yanli Zhang, Jin Liu, Raghuveer S. Makala, Johann Alsmeier | 2016-07-19 |
| 9379185 | Method of forming channel region dopant control in fin field effect transistor | Brian J. Greene, Arvind Kumar | 2016-06-28 |
| 9190418 | Junction butting in SOI transistor with embedded source/drain | Anthony I. Chou, Arvind Kumar, Robert R. Robison | 2015-11-17 |
| 9171758 | Method of forming transistor contacts | Woo-Hyeong Lee, Aimin Xing | 2015-10-27 |
| 8952460 | Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices | MaryJane Brodsky, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan, Shreesh Narasimha +1 more | 2015-02-10 |
| 8941189 | Fin-shaped field effect transistor (finFET) structures having multiple threshold voltages (Vt) and method of forming | Benjamin Cipriany, Brian J. Greene, Arvind Kumar | 2015-01-27 |
| 8853792 | Transistors and semiconductor devices with oxygen-diffusion barrier layers | James K. Schaeffer | 2014-10-07 |
| 8829616 | Method and structure for body contacted FET with reduced body resistance and source to drain contact leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha | 2014-09-09 |
| 8809152 | Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices | MaryJane Brodsky, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan, Shreesh Narasimha +1 more | 2014-08-19 |
| 8114739 | Semiconductor device with oxygen-diffusion barrier layer and method for fabricating same | James K. Schaeffer | 2012-02-14 |