Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Transistors on heterogeneous bonding layers

Transistors on heterogeneous bonding layers

US Patent 11532719 · Granted Dec 20, 2022

Estimated economic value: $12,719,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Nanowire transistor fabrication with hardmask layers2025
Nanowire transistor fabrication with hardmask layers2025
Double-sided integrated circuit transistor structures with depopulated bottom ch2025
Vertically spaced intra-level interconnect line metallization for integrated cir2025
Packaging architecture with intermediate routing layers2025
Integrated circuit structures with backside self-aligned penetrating conductive 2025
Subtractively patterned interconnect structures for integrated circuits2025
Inductor and transformer semiconductor devices using hybrid bonding technology2025
Monolithic chip stacking using a die with double-sided interconnect layers2025
Device, method and system to mitigate stress on hybrid bonds in a multi-tier arr2025
Conductive contacts wrapped around epitaxial source or drain regions2025
SRAM with P-type access transistors and complementary field-effect transistor te2025