Issued Patents All Time
Showing 526–550 of 1,397 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8063454 | Semiconductor structures including a movable switching element and systems including same | Chandra Mouli | 2011-11-22 |
| 8058130 | Method of forming a nitrogen-enriched region within silicon-oxide-containing masses | John T. Moore, Neal R. Rueger | 2011-11-15 |
| 8057686 | Nanotube separation methods | — | 2011-11-15 |
| 8052075 | Method for purification of semiconducting single wall nanotubes | Eugene P. Marsh | 2011-11-08 |
| 8049514 | Integrated circuit inspection system | Neal R. Rueger | 2011-11-01 |
| 8048812 | Pitch reduced patterns relative to photolithography features | Luan C. Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah +7 more | 2011-11-01 |
| 8048755 | Resistive memory and methods of processing resistive memory | John Smythe | 2011-11-01 |
| 8043975 | Silicon dioxide deposition methods using at least ozone and TEOS as deposition precursors | John Smythe | 2011-10-25 |
| 8043964 | Method for providing electrical connections to spaced conductive lines | Scott E. Sills | 2011-10-25 |
| 8039399 | Methods of forming patterns utilizing lithography and spacers | Ardavan Niroomand, Mark Kiehlbauch, Scott E. Sills | 2011-10-18 |
| 8035129 | Integrated circuitry | Nirmal Ramaswamy, Cem Basceri, Eric Blomiley | 2011-10-11 |
| 8034655 | Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays | John Smythe, Bhaskar Srinivasan | 2011-10-11 |
| 8034315 | Methods of forming devices comprising carbon nanotubes | Nishant Sinha, Eugene P. Marsh, Neil Greeley, John Smythe | 2011-10-11 |
| 8029858 | Methods of forming material on a substrate, and a method of forming a field effect transistor gate oxide on a substrate | — | 2011-10-04 |
| 8026501 | Method of removing or deposting material on a surface including material selected to decorate a particle on the surface for imaging | Mark Williamson, Paul M. Johnson, Shawn D. Lyonsmith, Justin R. Arrington | 2011-09-27 |
| 8022385 | Memory devices with buried lines | Fernando Gonzalez, Mike Violette | 2011-09-20 |
| 8021897 | Methods of fabricating a cross point memory array | Scott E. Sills | 2011-09-20 |
| 8017481 | Methods of forming nanoscale floating gate | D. V. Nirmal Ramaswamy | 2011-09-13 |
| 8011296 | Supercritical fluid-assisted direct write for printing integrated circuits | Cem Basceri | 2011-09-06 |
| 8008162 | Select devices including an open volume, memory devices and systems including same, and methods for forming same | Bhaskar Srinivasan | 2011-08-30 |
| 8003542 | Multiple spacer steps for pitch multiplication | Sanket Sant, Neal R. Rueger | 2011-08-23 |
| 8003310 | Masking techniques and templates for dense semiconductor fabrication | Ardavan Niroomand | 2011-08-23 |
| 7999328 | Isolation trench having first and second trench areas of different widths | Sukesh Sandhu | 2011-08-16 |
| 7989349 | Methods of manufacturing nanotubes having controlled characteristics | Terry L. Gilton | 2011-08-02 |
| 7985692 | Method to reduce charge buildup during high aspect ratio contact etch | Max Hineman, Daniel A. Steckert, Jingyi Bai, Shane J. Trapp, Tony Schrock | 2011-07-26 |