Issued Patents All Time
Showing 25 most recent of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11462648 | Fin-based Schottky diode for integrated circuit (IC) products and methods of making such a Schottky diode | Jagar Singh | 2022-10-04 |
| 11195947 | Semiconductor device with doped region adjacent isolation structure in extension region | Jagar Singh, Luigi Pantisano, Anvitha Shampur, Frank Scott Johnson | 2021-12-07 |
| 11127818 | High voltage transistor with fin source/drain regions and trench gate structure | Jagar Singh | 2021-09-21 |
| 10644157 | Fin-type field effect transistors with uniform channel lengths and below-channel isolation on bulk semiconductor substrates and methods | Julien Frougier, Ruilong Xie, Andreas Knorr | 2020-05-05 |
| 10483172 | Transistor device structures with retrograde wells in CMOS applications | Vara Govindeswara Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna +2 more | 2019-11-19 |
| 10347748 | Methods of forming source/drain regions on FinFET devices | Shesh Mani Pandey, Muhammad Tawhidur Rahman | 2019-07-09 |
| 9966313 | FinFET device and method of manufacturing | Shesh Mani Pandey, Baofu Zhu | 2018-05-08 |
| 9935112 | SRAM cell having dual pass gate transistors and method of making the same | Hui Zang | 2018-04-03 |
| 9852954 | Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures | Vara Govindeswara Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna +2 more | 2017-12-26 |
| 9576952 | Integrated circuits with varying gate structures and fabrication methods | Manoj Joshi, Manfred Eller, Richard J. Carter | 2017-02-21 |
| 9508743 | Dual three-dimensional and RF semiconductor devices using local SOI | Jagar Singh | 2016-11-29 |
| 9455201 | Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits | Manoj Joshi, Manfred Eller, Rohit Pal, Richard J. Carter, Bongki Lee +1 more | 2016-09-27 |
| 9437740 | Epitaxially forming a set of fins in a semiconductor device | Johannes M. van Meer, Michael Hargrove, Christian Gruensfelder, Yanxiang Liu | 2016-09-06 |
| 9362280 | Semiconductor devices with different dielectric thicknesses | Gauri Karve, Mark D. Hall | 2016-06-07 |
| 9362357 | Blanket EPI super steep retrograde well formation without Si recess | Laegu Kang, Vara Govindeswara Reddy Vakada, Michael Ganz, Yi Qi, Puneet Khanna +1 more | 2016-06-07 |
| 9362180 | Integrated circuit having multiple threshold voltages | Bongki Lee, Jin Ping Liu, Manoj Joshi, Manfred Eller, Rohit Pal +1 more | 2016-06-07 |
| 9209181 | Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures | Vara Govindeswara Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna +2 more | 2015-12-08 |
| 9196548 | Methods of using a trench salicide routing layer | Mahbub Rashed, David Doman, Navneet Jain, Subramani Kengeri, Suresh Venkatesan | 2015-11-24 |
| 9099380 | Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device | Vara Govindeswara Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna +1 more | 2015-08-04 |
| 9099492 | Methods of forming replacement gate structures with a recessed channel | Kuldeep Amarnath, Michael Hargrove | 2015-08-04 |
| 9099525 | Blanket EPI super steep retrograde well formation without Si recess | Laegu Kang, Vara Govindeswara Reddy Vakada, Michael Ganz, Yi Qi, Puneet Khanna +1 more | 2015-08-04 |
| 9040404 | Replacement metal gate structure for CMOS device | Takashi Ando, Kisik Choi | 2015-05-26 |
| 9034737 | Epitaxially forming a set of fins in a semiconductor device | Johannes M. van Meer, Michael Hargrove, Christian Gruensfelder, Yanxiang Liu | 2015-05-19 |
| 8916442 | Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device | Vara Govindeswara Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna +1 more | 2014-12-23 |
| 8809178 | Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents | Yanxiang Liu, Michael Hargrove, Xiaodong Yang, Hans Van Meer, Laegu Kang +1 more | 2014-08-19 |