MW

Mary E. Weybright

IBM: 19 patents #5,782 of 70,183Top 9%
Infineon Technologies Ag: 3 patents #2,452 of 7,486Top 35%
AS Adeia Semiconductor Solutions: 1 patents #22 of 57Top 40%
SA Siemens Aktiengesellschaft: 1 patents #10,653 of 22,248Top 50%
Overall (All Time): #203,378 of 4,157,543Top 5%
21
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
RE49794 SRAM design to facilitate single fin cut in double sidewall image transfer process Robert C. Wong 2024-01-09
10096521 SRAM design to facilitate single fin cut in double sidewall image transfer process Robert C. Wong 2018-10-09
9564446 SRAM design to facilitate single fin cut in double sidewall image transfer process Robert C. Wong 2017-02-07
6930004 Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scaling Geng Wang, Kevin McStay, Yujun Li, Dureseti Chidambarrao 2005-08-16
6724053 PMOSFET device with localized nitrogen sidewall implantation Rama Divakaruni, Ryota Katsumata, Giuseppe La Rosa, Rajesh Rengarajan 2004-04-20
6670667 Asymmetric gates for high density DRAM Ramachandra Divakaruni, Wayne F. Ellis, Jack A. Mandelman 2003-12-30
6656798 Gate processing method with reduced gate oxide corner and edge thinning Helmut Tews, Oleg Gluschenkov 2003-12-02
6548357 Modified gate processing for optimized definition of array and logic devices on same chip Gary B. Bronner, Richard A. Conti, Ramachandra Divakaruni, Jeffrey P. Gambino, Peter D. Hoh +1 more 2003-04-15
6504210 Fully encapsulated damascene gates for Gigabit DRAMs Ramachandra Divakaruni, Jeffrey P. Gambino, Jack A. Mandelman, Viraj Y. Sardesai 2003-01-07
6458646 Asymmetric gates for high density DRAM Ramachandra Divakaruni, Wayne F. Ellis, Jack A. Mandelman 2002-10-01
6403423 Modified gate processing for optimized definition of array and logic devices on same chip Gary B. Bronner, Richard A. Conti, Ramachandra Divakaruni, Jeffrey P. Gambino, Peter D. Hoh +1 more 2002-06-11
6388294 Integrated circuit using damascene gate structure Carl Radens, Gary B. Bronner 2002-05-14
6380027 Dual tox trench dram structures and process using V-groove Toshiharu Furukawa, Jeffrey P. Gambino, Edward W. Kiewra, Jack A. Mandelman, Carl Radens +1 more 2002-04-30
6346734 Modified gate conductor processing for poly length control in high density DRAMS Ramachandra Divakaruni 2002-02-12
6326260 Gate prespacers for high density, high performance DRAMs Ramachandra Divakaruni, James W. Adkisson, Scott D. Halle, Jeffrey P. Gambino, Heon Lee 2001-12-04
6261972 Dual gate oxide process for uniform oxide thickness Helmut Tews, Stephan Kudelka, Oleg Gluschenkov, Suri Hegde 2001-07-17
6197632 Method for dual sidewall oxidation in high density, high performance DRAMS Gary B. Bronner, Rama Divakaruni, Scott D. Halle, Dale W. Martin, Rajesh Rengarajan 2001-03-06
6194301 Method of fabricating an integrated circuit of logic and memory using damascene gate structure Carl Radens, Gary B. Bronner 2001-02-27
6190979 Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill Carl Radens 2001-02-20
6180975 Depletion strap semiconductor memory device Carl Radens 2001-01-30
6096664 Method of manufacturing semiconductor structures including a pair of MOSFETs Thomas Rupp, Stephan Kudelka, Jeffrey P. Gambino 2000-08-01