Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7895487 | Scan chain diagnostics using logic paths | Leah Pastel | 2011-02-22 |
| 7752514 | Methods and apparatus for testing a scan chain to isolate defects | William V. Huott, Maroun Kassab, Franco Motika | 2010-07-06 |
| 7558999 | Learning based logic diagnosis | James W. Adkisson, John M. Cohn, Maroun Kassab, Leah Pfeifer Pastel, David E. Sweenor | 2009-07-07 |
| 7434130 | Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection | William V. Huott, Franco Motika, Leah Pastel | 2008-10-07 |
| 7313744 | Methods and apparatus for testing a scan chain to isolate defects | William V. Huott, Maroun Kassab, Franco Motika | 2007-12-25 |
| 7240261 | Scan chain diagnostics using logic paths | Leah Pastel | 2007-07-03 |
| 7230335 | Inspection methods and structures for visualizing and/or detecting specific chip structures | Jerome L. Cann, Steven J. Holmes, Cherie R. Kagan, Leah Pastel, Paul William Pastel +2 more | 2007-06-12 |
| 7194706 | Designing scan chains with specific parameter sensitivities to identify process defects | James W. Adkisson, Greg Bazan, John M. Cohn, Matthew S. Grady, Mark D. Jaffe +5 more | 2007-03-20 |
| 7139950 | Segmented scan chains with dynamic reconfigurations | Leah Pastel | 2006-11-21 |
| 7089514 | Defect diagnosis for semiconductor integrated circuits | James W. Adkisson, Greg Bazan, John M. Cohn, Francis Gravel, Phillip J. Nigh +4 more | 2006-08-08 |
| 6954916 | Methodology for fixing Qcrit at design timing impact | Kerry Bernstein, Philip G. Emma, Paul D. Kartschoke, Norman J. Rohrer | 2005-10-11 |
| 6931580 | Rapid fail analysis of embedded objects | Kevin J. Barcomb, Mark F. Olive, Kevin C. Quandt | 2005-08-16 |
| 6901542 | Internal cache for on chip test data storage | Thomas Bartenstein, L. Farnsworth, Douglas C. Heaberlin, Edward E. Horton, III, Leah Pastel +3 more | 2005-05-31 |
| 6880136 | Method to detect systematic defects in VLSI manufacturing | Maroun Kassab, Leah Pastel | 2005-04-12 |
| 6865501 | Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection | William V. Huott, Franco Motika, Leah Pfeifer Pastel | 2005-03-08 |
| 6785413 | Rapid defect analysis by placement of tester fail data | Kevin J. Barcomb, Kevin C. Quandt | 2004-08-31 |
| 6721914 | Diagnosis of combinational logic circuit failures | Thomas Bartenstein, Douglas C. Heaberlin | 2004-04-13 |
| 6675323 | Incremental fault dictionary | Thomas Bartenstein, Douglas C. Heaberlin, Thomas F. Mechler, Leah Pastel, Glen E. Richard +1 more | 2004-01-06 |
| 6671644 | Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection | William V. Huott, Franco Motika, Leah Pastel | 2003-12-30 |
| 6519725 | Diagnosis of RAMS using functional patterns | Ya-Chieh Lai | 2003-02-11 |
| 6170078 | Fault simulation using dynamically alterable behavioral models | Mark A. Erle, Matthew C. Graf, Zaifu Zhang | 2001-01-02 |
| 6125461 | Method for identifying long paths in integrated circuits | Daniel R. Knebel, Phillip J. Nigh, Pia Naoko Sanda, Xiaodong Xiao | 2000-09-26 |
| 5297151 | Adjustable weighted random test pattern generator for logic circuits | Matthias Gruetzner, Sandip Kundu, Cordt Starke | 1994-03-22 |
| 4726023 | Determination of testability of combined logic end memory by ignoring memory | John L. Carter, Thomas W. Williams | 1988-02-16 |