TB

Thomas Bartenstein

CS Cadence Design Systems: 6 patents #235 of 2,263Top 15%
IBM: 3 patents #26,272 of 70,183Top 40%
Overall (All Time): #516,743 of 4,157,543Top 15%
10
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8402421 Method and system for subnet defect diagnostics through fault compositing Joseph Michael Swenton 2013-03-19
8397113 Method and system for identifying power defects using test pattern switching activity Patrick Gallagher 2013-03-12
8190953 Method and system for selecting test vectors in statistical volume diagnosis using failed test data Sameer H. Chakravarthy, Ratan Singh, Joseph Michael Swenton, Shaleen Bhabu 2012-05-29
8120378 System to control insertion of care-bits in an IC test vector improved optical probing Joseph Michael Swenton, Richard Schoonover, David Sliwinski 2012-02-21
7821276 Method and article of manufacture to generate IC test vector for synchronized physical probing Joseph Michael Swenton, Richard Schoonover, David Sliwinski 2010-10-26
7496816 Isolating the location of defects in scan chains Joseph Michael Swenton, David Sliwinski 2009-02-24
6901542 Internal cache for on chip test data storage L. Farnsworth, Douglas C. Heaberlin, Edward E. Horton, III, Leendert M. Huisman, Leah Pastel +3 more 2005-05-31
6721914 Diagnosis of combinational logic circuit failures Douglas C. Heaberlin, Leendert M. Huisman 2004-04-13
6708306 Method for diagnosing failures using invariant analysis Joseph Michael Swenton 2004-03-16
6675323 Incremental fault dictionary Douglas C. Heaberlin, Leendert M. Huisman, Thomas F. Mechler, Leah Pastel, Glen E. Richard +1 more 2004-01-06