Issued Patents All Time
Showing 25 most recent of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10211172 | Wafer-based electronic component packaging | Anuranjan Srivastava | 2019-02-19 |
| 10056294 | Techniques for adhesive control between a substrate and a die | Vivek Swaminathan Sridharan, Srikanth Kulkarni | 2018-08-21 |
| 9882075 | Light sensor with vertical diode junctions | Nicole D. Kerness, Christopher F. Edwards, Joy T. Jones, Pirooz Parvarandeh | 2018-01-30 |
| 9704809 | Fan-out and heterogeneous packaging of electronic components | Arkadii V. Samoilov, Pirooz Parvarandeh, Amit S. Kelkar | 2017-07-11 |
| 9608130 | Semiconductor device having trench capacitor structure integrated therein | Joseph P. Ellul, Edward Martin Godshalk, Kiyoko Ikeuchi, Anuranjan Srivastava | 2017-03-28 |
| 9520462 | Semiconductor device having capacitor integrated therein | Joseph P. Ellul, Anuranjan Srivastava, Kiyoko Ikeuchi, Scott W. Barry | 2016-12-13 |
| 9196672 | Semiconductor device having capacitor integrated therein | Joseph P. Ellul, Anuranjan Srivastava, Kiyoko Ikeuchi, Scott W. Barry | 2015-11-24 |
| 8847365 | Inductors and methods for integrated circuits | Joseph P. Ellul, Edward Martin Godshalk, Albert Bergemont | 2014-09-30 |
| 8344478 | Inductors having inductor axis parallel to substrate surface | Joseph P. Ellul, Edward Martin Godshalk, Albert Bergemont | 2013-01-01 |
| 8243021 | Slide and rotate display configurations for a handheld computing device | Rick Feightner, Wah Yiu Kwong, Katherine Mills, George K. Korinsky | 2012-08-14 |
| 7943473 | Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3D wafer-to-wafer modular integration scheme | Joseph P. Ellul, Albert Bergemont | 2011-05-17 |
| 6607962 | Globally planarized backend compatible thin film resistor contact/interconnect process | Viktor Zekeriya | 2003-08-19 |
| 6522013 | Punch-through via with conformal barrier liner | Robert Chen, Jeffrey A. Shields, Robert Dawson | 2003-02-18 |
| 6492258 | METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-&mgr;M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY | Minh Van Ngo, Paul R. Besser, Matthew S. Buynoski, John Caffall, Nick Maccrae +1 more | 2002-12-10 |
| 6472751 | H2 diffusion barrier formation by nitrogen incorporation in oxide layer | Robert Chen, Jeffrey A. Shields, Robert Dawson | 2002-10-29 |
| 6351013 | Low-K sub spacer pocket formation for gate capacitance reduction | Scott Luning, David Wu | 2002-02-26 |
| 6329718 | Method for reducing stress-induced voids for 0.25m.mu. and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby | Minh Van Ngo, Paul R. Besser, Matthew S. Buynoski, John Caffall, Nick Maccrae +1 more | 2001-12-11 |
| 6319859 | Borderless vias with HSQ gap filled metal patterns having high etching resistance | — | 2001-11-20 |
| 6232223 | High integrity borderless vias with protective sidewall spacer | Sunil Mehta | 2001-05-15 |
| 6232221 | Borderless vias | Sunil Mehta, Andre Stolmeijer | 2001-05-15 |
| 6194328 | H2 diffusion barrier formation by nitrogen incorporation in oxide layer | Robert Chen, Jeffrey A. Shields, Robert Dawson | 2001-02-27 |
| 6163818 | Streaming memory controller for a PCI bus | Uoc H. Nguyen, Otto Sperber, David K. Bovaird | 2000-12-19 |
| 6133142 | Lower metal feature profile with overhanging ARC layer to improve robustness of borderless vias | Jeff Shields | 2000-10-17 |
| 6100179 | Electromigration resistant patterned metal layer gap filled with HSQ | — | 2000-08-08 |
| 6097090 | High integrity vias | Sunil Mehta, Andre Stolmeijer | 2000-08-01 |