Issued Patents All Time
Showing 126–150 of 219 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9812365 | Methods of cutting gate structures on transistor devices | Haigou Huang, Xusheng Wu, Ruilong Xie, Stan Tsai | 2017-11-07 |
| 9806022 | Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions | — | 2017-10-31 |
| 9799776 | Semi-floating gate FET | Qing Liu | 2017-10-24 |
| 9799751 | Methods of forming a gate structure on a vertical transistor device | Steven Bentley, Kwan-Yong Lim | 2017-10-24 |
| 9786551 | Trench structure for high performance interconnection lines of different resistivity and method of making same | Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard S. Wise | 2017-10-10 |
| 9773708 | Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI | Steven Bentley, Kwan-Yong Lim | 2017-09-26 |
| 9759861 | Hybrid photonic and electronic integrated circuits | — | 2017-09-12 |
| 9761491 | Self-aligned deep contact for vertical FET | Haigou Huang, Xusheng Wu | 2017-09-12 |
| 9755051 | Embedded shape sige for strained channel transistors | Pietro Montanini | 2017-09-05 |
| 9748356 | Threshold adjustment for quantum dot array devices with metal source and drain | — | 2017-08-29 |
| 9741613 | Method for producing self-aligned line end vias and related device | Carl Radens, Lawrence A. Clevenger | 2017-08-22 |
| 9741609 | Middle of line cobalt interconnection | Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran | 2017-08-22 |
| 9730596 | Low power biological sensing system | — | 2017-08-15 |
| 9711649 | Transistors incorporating metal quantum dots into doped source and drain regions | — | 2017-07-18 |
| 9704991 | Gate height and spacer uniformity | Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran | 2017-07-11 |
| 9685456 | Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method | — | 2017-06-20 |
| 9679847 | Self-aligned bottom up gate contact and top down source-drain contact structure in the premetallization dielectric or interlevel dielectric layer of an integrated circuit | — | 2017-06-13 |
| 9659818 | Forming self-aligned dual patterning mandrel and non-mandrel interconnects | Lawrence A. Clevenger, Carl Radens | 2017-05-23 |
| 9660028 | Stacked transistors with different channel widths | Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian Pranatharthiharan | 2017-05-23 |
| 9660015 | Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions | — | 2017-05-23 |
| 9659820 | Interconnect structure having large self-aligned vias | Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard S. Wise, Akil Khamisi Sutton +2 more | 2017-05-23 |
| 9658523 | Interconnect structure having large self-aligned vias | Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard S. Wise, Terry A. Spooner +1 more | 2017-05-23 |
| 9653585 | Vertical gate-all-around TFET | — | 2017-05-16 |
| 9646939 | Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same | Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Byoung Youp Kim, Walter Kleemeier | 2017-05-09 |
| 9640636 | Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device | Steven Bentley, Kwan-Yong Lim, Hiroaki Niimi | 2017-05-02 |