Issued Patents All Time
Showing 76–100 of 219 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10319647 | Semiconductor structure with overlapping fins having different directions, and methods of fabricating the same | Qing Liu | 2019-06-11 |
| 10319630 | Encapsulated damascene interconnect structure for integrated circuits | Lawrence A. Clevenger, Carl Radens, Yiheng Xu | 2019-06-11 |
| 10312261 | Transistor with self-aligned source and drain contacts and method of making same | — | 2019-06-04 |
| 10304815 | Self-aligned three dimensional chip stack and method for making the same | Lawrence A. Clevenger, Carl Radens, Yiheng Xu | 2019-05-28 |
| 10269812 | Forming contacts for VFETs | Ruilong Xie, Lars Liebmann, Daniel Chanemougame, Chanro Park, Steven Bentley +1 more | 2019-04-23 |
| 10256351 | Semi-floating gate FET | Qing Liu | 2019-04-09 |
| 10249568 | Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions | — | 2019-04-02 |
| 10249496 | Narrowed feature formation during a double patterning process | Jiehui Shu, Xusheng Yu, Xiaoqiang Zhang | 2019-04-02 |
| 10247881 | Hybrid photonic and electronic integrated circuits | — | 2019-04-02 |
| 10242911 | Forming self-aligned vias and air-gaps in semiconductor fabrication | Lawrence A. Clevenger, Carl Radens | 2019-03-26 |
| 10242862 | Post-CMP hybrid wafer cleaning technique | — | 2019-03-26 |
| 10229999 | Methods of forming upper source/drain regions on a vertical transistor device | Xusheng Wu, Haigou Huang, Jiehui Shu | 2019-03-12 |
| 10217846 | Vertical field effect transistor formation with critical dimension control | Ruilong Xie, Steven Bentley, Min Gyu Sung, Chanro Park, Steven R. Soss +8 more | 2019-02-26 |
| 10211257 | High density resistive random access memory (RRAM) | Qing Liu | 2019-02-19 |
| 10199505 | Transistors incorporating metal quantum dots into doped source and drain regions | — | 2019-02-05 |
| 10157832 | Integrated circuit structure including via interconnect structure abutting lateral ends of metal lines and methods of forming same | Carl Radens, Lawrence A. Clevenger | 2018-12-18 |
| 10128327 | DRAM interconnect structure having ferroelectric capacitors exhibiting negative capacitance | — | 2018-11-13 |
| 10121874 | Self-aligned bottom up gate contact and top down source-drain contact structure in the premetallization dielectric or interlevel dielectric layer of an integrated circuit | — | 2018-11-06 |
| 10115633 | Method for producing self-aligned line end vias and related device | Carl Radens, Lawrence A. Clevenger | 2018-10-30 |
| 10109505 | Dual medium filter for ion and particle filtering during semiconductor processing | Laertis Economikos, Adam Ticknor, Wei-Tsu Tseng | 2018-10-23 |
| 10103252 | Vertical junction FinFET device and method for manufacture | Qing Liu | 2018-10-16 |
| 10103245 | Embedded shape sige for strained channel transistors | Pietro Montanini | 2018-10-16 |
| 10084080 | Vertical tunneling FinFET | Qing Liu | 2018-09-25 |
| 10074606 | Via, trench or contact structure in the metallization, prematallization dielectric or interlevel dielectric layers of an integrated circuit | — | 2018-09-11 |
| 10039462 | Low power biological sensing system | — | 2018-08-07 |