Issued Patents All Time
Showing 26–50 of 219 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10985063 | Semiconductor device with local connection | Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, Junli Wang | 2021-04-20 |
| 10964551 | Control of wafer surface charge during CMP | — | 2021-03-30 |
| 10950722 | Vertical gate all-around transistor | Carl Radens, Lawrence A. Clevenger, Yiheng Xu | 2021-03-16 |
| 10943837 | Device having overlapping semiconductor fins oriented in different directions | Qing Liu | 2021-03-09 |
| 10937811 | Integrated circuit devices and fabrication techniques | — | 2021-03-02 |
| 10930553 | Forming self-aligned vias and air-gaps in semiconductor fabrication | Lawrence A. Clevenger, Carl Radens | 2021-02-23 |
| 10910385 | Vertical gate-all-around TFET | — | 2021-02-02 |
| 10892344 | Atomic layer deposition of selected molecular clusters | — | 2021-01-12 |
| 10892281 | Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method | — | 2021-01-12 |
| 10861984 | Integrated cantilever switch | Qing Liu | 2020-12-08 |
| 10833204 | Multiple width nanosheet devices | Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, Junli Wang | 2020-11-10 |
| 10816729 | Hybrid photonic and electronic integrated circuits | — | 2020-10-27 |
| 10804377 | SOI FinFET transistor with strained channel | — | 2020-10-13 |
| 10741698 | Semi-floating gate FET | Qing Liu | 2020-08-11 |
| 10741449 | Stacked transistors with different channel widths | Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian Pranatharthiharan | 2020-08-11 |
| 10734289 | Method for forming strained fin channel devices | Kangguo Cheng, Junli Wang, Lawrence A. Clevenger, Carl Radens | 2020-08-04 |
| 10700194 | Vertical tunneling FinFET | Qing Liu | 2020-06-30 |
| 10700214 | Overturned thin film device with self-aligned gate and source/drain (S/D) contacts | Lawrence A. Clevenger, Carl Radens, Yiheng Xu | 2020-06-30 |
| 10680112 | Gate all around vacuum channel transistor | — | 2020-06-09 |
| 10658459 | Nanosheet transistor with robust source/drain isolation from substrate | Robin Hsin Kuo Chao, Kangguo Cheng, Cheng Chi, Ruilong Xie | 2020-05-19 |
| 10651293 | Methods of simultaneously forming bottom and top spacers on a vertical transistor device | — | 2020-05-12 |
| 10629538 | Modular interconnects for gate-all-around transistors | — | 2020-04-21 |
| 10627720 | Overlay mark structures | Lei Sun, Shao Beng Law, Guoxiang Ning, Xunyuan Zhang, Ruilong Xie | 2020-04-21 |
| 10615177 | Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method | — | 2020-04-07 |
| 10615125 | Device and method for alignment of vertically stacked wafers and die | Walter Kleemeier, Paul Ferreira, Ronald K. Sampson | 2020-04-07 |