JL

Joe Lee

IBM: 25 patents #4,217 of 70,183Top 7%
TE Tessera: 8 patents #54 of 271Top 20%
SS Stmicroelectronics Sa: 5 patents #285 of 1,676Top 20%
TL Tokyo Electron Limited: 4 patents #1,723 of 5,567Top 35%
ZE Zeon: 2 patents #301 of 734Top 45%
AS Adeia Semiconductor Solutions: 1 patents #22 of 57Top 40%
Overall (All Time): #96,216 of 4,157,543Top 3%
35
Patents All Time

Issued Patents All Time

Showing 25 most recent of 35 patents

Patent #TitleCo-InventorsDate
12400859 Metal hard mask for precise tuning of mandrels Yann Mignot, Christopher J. Penny, Koichi Motoyama 2025-08-26
12266607 Bottom barrier free interconnects without voids Kenneth Chun Kuen Cheng, Koichi Motoyama, Kisik Choi, Cornelius Brown Peethala, Hosadurga Shobha 2025-04-01
12183634 Selective recessing to form a fully aligned via Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Thedorus E. Standaert 2024-12-31
12033892 Structure and method to improve FAV RIE process margin and electromigration Benjamin D. Briggs, Theodorus E. Standaert 2024-07-09
11837501 Selective recessing to form a fully aligned via Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Theodorus E. Standaert 2023-12-05
11721578 Split ash processes for via formation to suppress damage to low-K layers Yen-Tien Lu, Angelique Raley 2023-08-08
11710658 Structure and method to improve FAV RIE process margin and Electromigration Benjamin D. Briggs, Theodorus E. Standaert 2023-07-25
11257717 Selective recessing to form a fully aligned via Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Theodorus E. Standaert 2022-02-22
11164815 Bottom barrier free interconnects without voids Kenneth Chun Kuen Cheng, Koichi Motoyama, Kisik Choi, Cornelius Brown Peethala, Hosadurga Shobha 2021-11-02
11037822 Svia using a single damascene interconnect Yann Mignot, Muthumanickam Sankarapandian, Yongan Xu 2021-06-15
10985056 Structure and method to improve FAV RIE process margin and Electromigration Benjamin D. Briggs, Theodorus E. Standaert 2021-04-20
10957584 Structure and method to improve FAV RIE process margin and electromigration Benjamin D. Briggs, Theodorus E. Standaert 2021-03-23
10832952 Selective recessing to form a fully aligned via Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Theodorus E. Standaert 2020-11-10
10672705 Method of forming a straight via profile with precise critical dimension control Yongan Xu, Junli Wang, Yann Mignot 2020-06-02
10643859 Hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication Robert L. Bruce, Eric A. Joseph, Takefumi Suzuki 2020-05-05
10636706 Selective recessing to form a fully aligned via Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Theodorus E. Standaert 2020-04-28
10622301 Method of forming a straight via profile with precise critical dimension control Yongan Xu, Junli Wang, Yann Mignot 2020-04-14
10347825 Selective deposition and nitridization of bottom electrode metal for MRAM applications Benjamin D. Briggs, Christopher J. Penny, Michael Rizzolo, Chih-Chao Yang 2019-07-09
10312434 Selective deposition and nitridization of bottom electrode metal for MRAM applications Benjamin D. Briggs, Christopher J. Penny, Michael Rizzolo, Chih-Chao Yang 2019-06-04
10276436 Selective recessing to form a fully aligned via Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Theodorus E. Standaert 2019-04-30
10211138 Metal silicate spacers for fully aligned vias Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang 2019-02-19
10170416 Selective blocking boundary placement for circuit locations requiring electromigration short-length Benjamin D. Briggs, Elbert E. Huang, Christopher J. Penny 2019-01-01
10121676 Interconnects fabricated by hydrofluorocarbon gas-assisted plasma etch Robert L. Bruce, Eric A. Joseph, Takefumi Suzuki 2018-11-06
10049974 Metal silicate spacers for fully aligned vias Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang 2018-08-14
10020254 Integration of super via structure in BEOL Ruqiang Bao, Yann Mignot, Hosadurga Shobha, Junli Wang, Yongan Xu 2018-07-10