Issued Patents All Time
Showing 1–25 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10923427 | SOI wafers with buried dielectric layers to prevent CU diffusion | Anthony K. Stamper, Mukta G. Farooq | 2021-02-16 |
| 10242947 | SOI wafers with buried dielectric layers to prevent CU diffusion | Anthony K. Stamper, Mukta G. Farooq | 2019-03-26 |
| 10074562 | Self aligned contact structure | Rosa A. Orozco-Teran, Ravikumar Ramachandran, Russell H. Arndt, David L. Rath | 2018-09-11 |
| 10037911 | Device layer transfer with a preserved handle wafer section | Anthony K. Stamper, Mukta G. Farooq, Mark D. Jaffe, Randy L. Wolf | 2018-07-31 |
| 9966310 | Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same | Mukta G. Farooq, Anthony K. Stamper | 2018-05-08 |
| 9929085 | Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same | Mukta G. Farooq, Anthony K. Stamper | 2018-03-27 |
| 9892970 | Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same | Mukta G. Farooq, Anthony K. Stamper | 2018-02-13 |
| 9852959 | Corrosion resistant chip sidewall connection with crackstop and hermetic seal | Michael J. Shapiro, Natalia Borjemscaia, Vincent J. McGahay | 2017-12-26 |
| 9818637 | Device layer transfer with a preserved handle wafer section | Anthony K. Stamper, Mukta G. Farooq, Mark D. Jaffe, Randy L. Wolf | 2017-11-14 |
| 9812404 | Electrical connection around a crackstop structure | Michael J. Shapiro, Natalia Borjemscaia | 2017-11-07 |
| 9806025 | SOI wafers with buried dielectric layers to prevent Cu diffusion | Anthony K. Stamper, Mukta G. Farooq | 2017-10-31 |
| 9671215 | Wafer to wafer alignment | Mukta G. Farooq, Spyridon Skordas | 2017-06-06 |
| 9673176 | Metal to metal bonding for stacked (3D) integrated circuits | Tien-Jen Cheng, Mukta G. Farooq | 2017-06-06 |
| 9666563 | Metal to metal bonding for stacked (3D) integrated circuits | Tien-Jen Cheng, Mukta G. Farooq | 2017-05-30 |
| 9653432 | Metal to metal bonding for stacked (3D) integrated circuits | Tien-Jen Cheng, Mukta G. Farooq | 2017-05-16 |
| 9653431 | Metal to metal bonding for stacked (3D) integrated circuits | Tien-Jen Cheng, Mukta G. Farooq | 2017-05-16 |
| 9589806 | Integrated circuit with replacement gate stacks and method of forming same | Ruqiang Bao, Unoh Kwon, Huihang Dong | 2017-03-07 |
| 9553054 | Strain detection structures for bonded wafers and chips | Mukta G. Farooq, Erdem Kaltalioglu, Wei Lin, Spyridon Skordas, Kevin R. Winstel | 2017-01-24 |
| 9548244 | Self-aligned contact structure | Rosa A. Orozco-Teran, Ravikumar Ramachandran, Russell H. Arndt, David L. Rath | 2017-01-17 |
| 9515051 | Metal to metal bonding for stacked (3D) integrated circuits | Tien-Jen Cheng, Mukta G. Farooq | 2016-12-06 |
| 9461017 | Electronic package that includes a plurality of integrated circuit devices bonded in a three-dimensional stack arrangement | Mukta G. Farooq, Andrew H. Simon, Anthony K. Stamper | 2016-10-04 |
| 9418865 | Wet etching of silicon containing antireflective coatings | Gregory Nowling | 2016-08-16 |
| 9257336 | Bottom-up plating of through-substrate vias | Mukta G. Farooq, Troy L. Graves-Abe | 2016-02-09 |
| 9252053 | Self-aligned contact structure | Rosa A. Orozco-Teran, Ravikumar Ramachandran, Russell H. Arndt, David L. Rath | 2016-02-02 |
| 9153558 | Electromigration immune through-substrate vias | Ronald G. Filippi, Kevin Kolvenbach, Ping-Chuan Wang | 2015-10-06 |